• Journal of Internet Computing and Services
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• v.15 no.1
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• pp.171-178
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• 2014

This paper presents dynamic modelling of a virtual object in augmented reality environments when external forces are applied to the object in real-time fashion. In order to simulate a natural behavior of the object we employ the theory of Newtonian physics to construct motion equation of the object according to the varying external forces applied to the AR object. In dynamic modelling process, the physical interaction is taken placed between the augmented object and the physical object such as a haptic input device and the external forces are transferred to the object. The intrinsic properties of the augmented object are either rigid or elastically deformable (non-rigid) model. In case of the rigid object, the dynamic motion of the object is simulated when the augmented object is collided with by the haptic stick by considering linear momentum or angular momentum. In the case of the non-rigid object, the physics-based simulation approach is adopted since the elastically deformable models respond in a natural way to the external or internal forces and constraints. Depending on the characteristics of force caused by a user through a haptic interface and model's intrinsic properties, the virtual elastic object in AR is deformed naturally. In the simulation, we exploit standard mass-spring damper differential equation so called Newton's second law of motion to model deformable objects. From the experiments, we can successfully visualize the behavior of a virtual objects in AR based on the theorem of physics when the haptic device interact with the rigid or non-rigid virtual object.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.80-89
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.6
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• pp.43-54
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• 2016

The occurrence of cyber crime is on the rise every year, and the security control center, which should play a crucial role in monitoring and early response against the cyber attacks targeting various information systems, its importance has increased accordingly. Every endeavors to prevent cyber attacks is being attempted by information security personnel of government and financial sector's security control center, threat response Center, cyber terror response center, Cert Team, SOC(Security Operator Center) and else. The ordinary method to monitor cyber attacks consists of utilizing the security system or the network security device. It is anticipated, however, to be insufficient since this is simply one dimensional way of monitoring them based on signatures. There has been considerable improvement of the security control system and researchers also have conducted a number of studies on monitoring methods to prevent threats to security. In accordance with the environment changes from ESM to SIEM, the security control system is able to be provided with more input data as well as generate the correlation analysis which integrates the processed data, by extraction and parsing, into the potential scenarios of attack or threat. This article shows case studies how to detect the threat to security in effective ways, from the initial phase of the security control system to current SIEM circumstances. Furthermore, scenarios based security control systems rather than simple monitoring is introduced, and finally methods of producing the correlation analysis and its verification methods are presented. It is expected that this result contributes to the development of cyber attack monitoring system in other security centers.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.34-39
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• 2016

A low-voltage, low-power analog front-end IC for neural recording implant devices is presented. The proposed IC consists of a low-noise neural amplifier and a programmable active bandpass filter to process neural signals residing in the band of 1 Hz to 5 kHz. The neural amplifier is based on a source-degenerated folded-cascode operational transconductance amplifier (OTA) for good noise performance while the following bandpass filter utilizes a low-power current-mirror based OTA with programmable high-pass cutoff frequencies from 1 Hz to 300 Hz and low-pass cutoff frequencies from 300 Hz to 8 kHz. The total recording analog front-end provides 53.1 dB of voltage gain, $4.68{\mu}Vrms$ of integrated input referred noise within 1 Hz to 10 kHz, and noise efficiency factor of 3.67. The IC is designed using $18-{\mu}m$ CMOS process and consumes a total of $3.2{\mu}W$ at 1-V supply voltage. The layout area of the IC is $0.19 mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.32 no.1
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• pp.65-73
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• 2019

In order to increase the production efficiency of the ship and shorten the production cycle, it is important to evaluate the accuracy of the ship components efficiently during the drying cycle. The accuracy control of the block is important for shortening the ship process, reducing the cost, and improving the accuracy of the ship. Some systems have been developed and used mainly in large shipyards, but in some cases, they are measured and managed using conventional measuring instruments such as tape measure and beam, optical instruments as optical equipment, In order to perform accuracy control, these tools and equipment as well as equipment for recording measurement data and paper drawings for measuring the measurement position are inevitably combined. The measured results are managed by the accuracy control system through manual input or recording device. In this case, the measurement result is influenced by the work environment and the skill level of the worker. Also, in the measurement result management side, there are a human error about the lack of the measurement result creation, the lack of the management sheet management, And costs are lost in terms of efficiency due to consumption. The purpose of this study is to improve the working environment in the existing accuracy management process by using the augmented reality technology to visualize the measurement information on the actual block and to obtain the measurement information And a smart management system based on augmented reality that can effectively manage the accuracy management data through interworking with measurement equipment. We confirmed the applicability of the proposed system to the accuracy control through the prototype implementation.

• Journal of Korea Multimedia Society
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• v.15 no.10
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• pp.1196-1204
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• 2012

In this paper, a series of algorithms are proposed for controlling different kinds of multimedia contents and realizing interact between human and computer by using single input device. Human gesture recognition based on NUI is presented firstly in my paper. Since the image information we get it from camera is not sensitive for further processing, we transform it to YCbCr color space, and then morphological processing algorithm is used to delete unuseful noise. Boundary Energy and depth information is extracted for hand detection. After we receive the image of hand detection, PCA algorithm is used to recognize hand posture, difference image and moment method are used to detect hand centroid and extract trajectory of hand movement. 8 direction codes are defined for quantifying gesture trajectory, so the symbol value will be affirmed. Furthermore, HMM algorithm is used for hand gesture recognition based on the symbol value. According to series of methods we presented, we can control multimedia contents by using human gesture recognition. Through large numbers of experiments, the algorithms we presented have satisfying performance, hand detection rate is up to 94.25%, gesture recognition rate exceed 92.6%, hand posture recognition rate can achieve 85.86%, and face detection rate is up to 89.58%. According to these experiment results, we can control many kinds of multimedia contents on computer effectively, such as video player, MP3, e-book and so on.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.89-96
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• 2015

This paper presents a high efficiency, PSM/DCM/CCM triple mode boost DC-DC converter for mobile application. This device operates at Pulse-Skipping Mode(PSM) when it enters light load, and otherwise operate the operating frequency of 1.4MHz with Pulse-Width Modulation(PWM) mode. Especially in order to improve the efficiency during the Discontinuous-Conduction Mode(DCM) operation period, the reverse current prevention circuit and oscillations caused by the inductor and the parasitic capacitor to prevent the Ringing killer circuit is added. The input voltage of the boost converter ranges from 2.5V ~ 4.2V and it generates the output of 4.8V. The measurement results show that the boost converter provides a peak efficiency of 92% on CCM and 87% on DCM. And an efficiency-improving PWM operation raises the efficiency drop because of transition from PWM to PFM. The converter has been fabricated with a 0.18um Dongbu BCDMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.6
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• pp.97-104
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• 2010

In this paper, ICT (in circuit tester) inspection system and inspection algorithm is proposed and detects whether inferiority exists or not in the mounted device on the flexible PCB in cell phones or mobile display devices. The system is composed of PD (pin-driver) and GGM (ground guarding method). The structural characteristics of these flexible PCB are analyzed, which is needed to input or output the test signal. Test signal to investigate the characteristics of passive components is generated using modified circuit diagram and proposed inspection algorithm. PM (pin-map) is decided on the basis of circuit diagram and has the information about the kind of test signal to be applied and the pad number for the test signal to be connected. PD is designed to load a proper test signal for a specific pad and is adjusted according to PM so that the reconstructed circuit has minimum node and mash. The proposed ICT inspection system is realized using PD and GGM. Using the system, an experiment for each passive component is done to investigate the measurement accuracy of the developed system and an experiment for real flexible PCB model is done to verity the effectiveness of the system.