• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1092-1097
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• 2005

In this paper, we propose a low-power Booth multiplication which reduces the switching activities of partial products during multiplication process. Radix-4 Booth algorithm has a characteristic that produces the Booth encoded products with zero when input data have sequentially equal values (0 or 1). Therefore, partial products have higher chances of being zero when an input with a smaller effective dynamic range of two multiplication inputs is used as a multiplier data instead of a multiplicand. The proposed multiplier divides a multiplication expression into several multiplication expressions with smaller bits than those of an original input data, and each multiplication is computed independently for the Booth encoding. Finally, the results of each multiplication are added. This means that the proposed multiplier has a higher chance to have zero encoded products so that we can implement a low power multiplier with the smaller switching activity. Implementation results show the proposed multiplier can save maximally about $20\%$ power dissipation than a previous Booth multiplier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.5C
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• pp.384-392
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• 2012

Recently, much research on blind estimation of the interleaver parameters has been performed by using Gauss-Jordan elimination to find the linearity of the block channel code. When using Gauss-Jordan elimination, the input data to be calculated needs to run as long as the square multiple of the number of the interleaver period. Thus, it has a limit in estimating the interleaver parameters with insufficient input data. In this paper, we introduce and analyze an estimation algorithm which can estimate interleaver parameters by using only 15 percent of the input data length required in the above algorithm. The shorter length of input data to be calculated makes it possible to estimate the interleaver parameters even when limited data is received. In addition, a 80 percent reduction in the number of the interleaver period candidates increases the efficiency of analysis. It is also feasible to estimate both the type and size of the interleaver and the type of channel coding.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.698-701
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• 2002

Subspace analysis (which includes PCA) seeks for feature subspace (which corresponds to the eigenspace), given multivariate input data and has been widely used in computer vision and pattern recognition. Typically data space belongs to very high dimension, but only a few principal components need to be extracted. In this paper I present a fast sequential algorithm for subspace analysis or tracking. Useful behavior of the algorithm is confirmed by numerical experiments.

• Proceedings of the IEEK Conference
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• 2000.06d
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• pp.182-185
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• 2000

In this paper, we present a new adaptive filter structure which is based on polyphase decomposition of the filter to be adapted. This structure uses wavelet transform to acquire transform-domain coefficients of the input signal. With this coefficients RLS algorithm is used for adaptation. Particularly, using the polyphase parallel structure, we can trace the system which has very long impulse response with only increasing the subband, and show that computational savings can be achieved. The proposed structure was applied to system identification for performance estimation and compared with fullband adaptive filter.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2581-2584
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• 2003

In this paper, we propose a self-localization algorithm using vertical line segments. Indoor environment is consist of horizontal and vertical line features such as doors, furniture, and so on. From the input image, vertical line edges are detected by an edge operator, Then, line segments are obtained by projecting edge image vertically and detecting local maximum from the projected histogram. From the relation of horizontal position of line segments and the location of the robot, nonlinear equations are come out Localization is done by solving the equations by using Newton's method. Experimental results show that the proposed algorithm using one camera is simple and applicable to indoor environment.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.789-792
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• 2005

In this paper, we propose a method that applies pipeline architecture to parallel CRC circuits. We developed a logic partitioning algorithm for applying pipeline architecture. Our algorithm can be used for the polynomial and the input data width, both of arbitrary length and minimize the logic level. Design experiments show the superiority of our approach in reducing the delay in comparison with previous works.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.915-918
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• 2001

In this paper we study a new convergence behavior of the least mean fourth (LMF) algorithm where the error raised to the power of four is minimized for a multiple sinusoidal input and Gaussian measurement noise. Here we newly obtain the convergence equation for the sum of the mean of the squared weight errors, which indicates that the transient behavior can differ depending on the relative sizes of the Gaussian noise and the convergence constant. It should be noted that no similar results can be expected from the previous analysis by Walach and Widrow.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1025-1028
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• 1998

Hardware to implement the parallelized Floating-point rounding algorithm is described. For parallelized additions, we propose an addition module which has carry selection logic to generate two results accoring to the input valuse. A multiplication module for parallelized multiplications is also proposed to generate Sum and Carry bits as intermediate results. Since these modules process data in IEEE standard Floatingpoint double precision format, they are designed for 53-bit significands including hidden bits. Multiplication module is designed with a Booth multiplier and an array multiplier.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.145-148
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• 2000

ATM network is considered as best suitable technology for multimedia service in various aspects such as bandwidth, capability of traffic expandability and so on. In this paper, we suggested a buffer management algorithm in ATM network to improve overall network performance with threshold and auxiliary buffer whose input consists of superpositiI on of voice and multimedia data traffic. To evaluate the proposed buffer management algorithm simulations are executed with four priorities, that is delay and loss priorities and the results are proved that network throughput is improved better than the existing partial buffer method.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.705-708
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• 1998

In this paper, a new algorithm is proposed that the template matching is used to devide SOFM (self-organizig feature map) for fast learning and to extract features for considering input data types. In order to verify the superoprity of the proposed algorithm, applied to the recognition of handwritten numerals. Templates of handwritten numerals are created by a line of external-contact.