• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.10
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• pp.73-82
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• 2015

This paper proposes an ripple reduction algorithm and analyzes the effects of offset and scale errors generated by voltage sensor while measuring grid voltage in grid-tied single-phase inverters. Generally, the grid-connected inverter needs to detect the phase angle information by measuring grid voltage for synchronization, so that the single-phase inverter can be accurately driven based on estimated phase angle information. However, offset and scale errors are inevitably generated owing to the non-linear characteristics of voltage sensor and these errors affect that the phase angle includes 1st harmonic component under using SRF-PLL(Synchronous Reference Frame - Phase Locked Loop) system for detecting grid phase angle. Also, the performance of the overall system is degraded from the distorted phase angle including the specific harmonic component. As a result, in this paper, offset and scale error due to the voltage sensor in single-phase grid connected inverter under SRF-PLL is analyzed in detail and proportional resonant controller is used to reduce the ripples caused by the offset error. Especially, the integrator output of PI(Proportional Integral) controller in SRF-PLL is selected as an input signal of the proportional resonant controller. Simulation and experiment are performed to verify the effectiveness of the proposed algorithm.

• The Transactions of the Korea Information Processing Society
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• v.5 no.8
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• pp.2061-2074
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• 1998

In pattern recognition and image analysis upplications, a graph is a useful tool for complex obect representation and recognition. However it takes much time to pair proper nodes between the prototype graph and an input data graph. Futhermore it is difficult to decide whether the two graphs in a class are the same hecause real images are degradd in general by noise and other distortions. In this paper we propose a matching algorithm using a matrix. The matrix is suiable for simple and easily understood representation and enables the ordering and matching process to be convenient due to its predefined matrix manipulation. The nodes which constitute a gaph are ordered in the matrix by their geometrical positions and this makes it possible to save much comparison time for finding proper node pairs. for the classification, we defined a distance measure thatreflects the symbo's structural aspect that is the sum of the mode distance and the relation distance; the fornet is from the parameters describing the node shapes, the latter from the relations with othes node in the matrix. We also introduced a subdivision operation to compensate node merging which is mainly due t the prepreocessing error. The proposed method is applied to the recognition of musteal symbols and the result is given. The result shows that almost all, except heavily degraded symbols are recognized, and the recognition rate is approximately 95 percent.

• Journal of Korea Society of Industrial Information Systems
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• v.5 no.3
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• pp.117-124
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• 2000

A systolic array is a parallel processing system which consists of processing elements of basic computation capabilities, connected with regular and local communication lines. It has been known that a systolic array is on of effective systems to solve complicated communication problems occurred between densely connected neurons on ANN(Artificial Neural Network). In this paper, a systolic array simulator for the back-propagation ANN, which automatically constructs the proper systolic array for a given number of neurons of the ANN, is designed and constructed. With animation techniques of the simulators, it is easy for users to be able to examine the execution of the back-propagation algorithm on the designed systolic array step by step. Moreover the simulator can perform forward and backward operations of the back-propagation algorithm either in sequence or in parallel on the designed systolic array. Parallel execution can be performed by feeding continuous input patterns and by executing bidirectional propagations on all of processing elements of a systolic array at the same time.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.4
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• pp.139-149
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• 2003

In this paper a hardware design of area-efficient hash processor which implements MD5 algorithm using hardware sharing and carry-save addition schemes is described. To reduce area, the processor adopts hardware sharing scheme in which 1 step operation is divided into 2 substeps and then each substep is executed using the same hardware. Also to increase clock frequency, three serial additions of substep operation are transformed into two carry-save additions and one carry propagation addition. The MD5 hash processor is designed using 0.25 $\mu\textrm{m}$CMOS technology and consists of about 13,000 gates. From timing simulation results, the designed MD5 hash processor has 465 Mbps hash rates for 512-bit input message data under 120 MHz operating frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.2
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• pp.165-170
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• 2021

Machine learning has recently been applied to research in most areas. This is because the results of machine learning are not determined, but the learning of input data creates the objective function, which enables the determination of new data. In addition, the increase in accumulated data affects the accuracy of machine learning results. The data collected here is an important factor in machine learning. The proposed system is a convergence system of cloud systems and local fog systems for service delivery. Thus, the cloud system provides machine learning and infrastructure for services, while the fog system is located in the middle of the cloud and the user to collect and refine data. The data for this application shall be based on the Sensitive data generated by smart devices. The machine learning technique applied to this system uses SVM algorithm for classification and RNN algorithm for status recognition.

• Journal of the Korea Society of Computer and Information
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• v.26 no.11
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• pp.33-40
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• 2021

Due to advanced complex strategies, the complexity of information that a commander must analyze is increasing. An intelligent service that can analyze battlefield is needed for the commander's timely judgment. This service consists of extracting knowledge from battlefield information, building a knowledge base, and analyzing the battlefield information from the knowledge base. This paper extract information similar to an input query by embedding the knowledge base built in the 2^nd step. The transformation model is needed to generate the embedded knowledge base and uses the random-walk algorithm. The transformed information is embedding using Word2Vec, and Similar information is extracted through cosine similarity. In this paper, 980 sentences are generated from the open knowledge base and embedded as a 100-dimensional vector and it was confirmed that similar entities were extracted through cosine similarity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.546-552
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• 2000

The decoding of Turbo-Code relies on the application of a soft input/soft output decoders which can be realized using maximum-a-posteriori(MAP) symbol estimator[l]. Radix-2 MAP decoder can not be used for high speed communications because of a large number of interleaver block size N. This paper proposed a new simple method for radix-4 MAP decoder based on radix-2 MAP decoder in order to reduce the interleave block size. A branch metrics, forward and backward recursive functions are proposed for applying to radix-4 MAP structure with symbol interleaver. Radix-4 MAP decoder shall be illustratively described and its error performance capability shall be compared to conventional radix-2 MAP decoder in AWGN channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2264-2275
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• 1994

In this paper, image compression based on neural networks is presented with block classification and coding. Multilayer neural networks with error back-propagation learning algorithm are used to transform the normalized image date into the compressed hidden values by reducing spatial redundancies. Image compression can basically be achieved with smaller number of hidden neurons than the numbers of input and output neurons. Additionally, the image blocks can be grouped for adaptive compression rates depending on the characteristics of the complexity of the blocks in accordance with the sensitivity of the human visual system(HVS). The quantized output of the hidden neuron can also be entropy coded for an efficient transmission. In computer simulation, this approach lie in the good performances even with images outside the training set and about 25:1 compression rate was achieved using the entropy coding without much degradation of the reconstructed images.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1307-1311
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• 2006

In this paper, we propose new speech feature parameter using the Matrix Factorization for appearance part-based features of speech spectrum. The proposed parameter represents effective dimensional reduced data from multi-dimensional feature data through matrix factorization procedure under all of the matrix elements are the non-negative constraint. Reduced feature data presents p art-based features of input data. We verify about usefulness of NMF(Non-Negative Matrix Factorization) algorithm for speech feature extraction applying feature parameter that is got using NMF in Mel-scaled filter bank output. According to recognition experiment results, we confirm that proposed feature parameter is superior to MFCC(Mel-Frequency Cepstral Coefficient) in recognition performance that is used generally.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.3A
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• pp.135-140
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• 2012

This paper proposes a technology for performance enhancement of cyclic delay diversity OFDM system using frequency diversity. The frequency diversity in an OFDM system can be done as repetitive transmission of the same symbol on uncorrelated subcarrier, this makes modulation level larger according to the number of repetitive transmission for the comparison with the traditional transmission system. This technique, like cyclic delay diversity, has a benefit which it does not need any special subsidiary hardware irrespective of the increase of the number of transmitter. For the performance comparison, we simulate the proposed algorithm in multiple input single out channel environment, it shows a better performance enhancement in low dense modulation level in comparison with the traditional cyclic delay diversity OFDM system.