• Title/Summary/Keyword: Information input algorithm

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Cascaded H-Bridge Five Level Inverter for Grid Connected PV System using PID Controller

  • Sivagamasundari, M.S.;Mary, P. Melba
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.4
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    • pp.451-462
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    • 2016
  • Photovoltaic energy conversion becomes main focus of many researches due to its promising potential as source for future electricity and has many advantages than the other alternative energy sources like wind, solar, ocean, biomass, geothermal etc. In Photovoltaic power generation multilevel inverters play a vital role in power conversion. The three different topologies, diode-clamped (neutral-point clamped) inverter, capacitor-clamped (flying capacitor) inverter and cascaded h-bridge multilevel inverter are widely used in these multilevel inverters. Among the three topologies, cascaded h-bridge multilevel inverter is more suitable for photovoltaic applications since each pv array can act as a separate dc source for each h-bridge module. This paper presents a single phase Cascaded H-bridge five level inverter for grid-connected photovoltaic application using sinusoidal pulse width modulation technique. This inverter output voltage waveform reduces the harmonics in the generated current and the filtering effort at the input. The control strategy allows the independent control of each dc-link voltages and tracks the maximum power point of PV strings. This topology can inject to the grid sinusoidal input currents with unity power factor and achieves low harmonic distortion. A PID control algorithm is implemented in Arm Processor LPC2148. The validity of the proposed inverter is verified through simulation and is implemented in a single phase 100W prototype. The results of hardware are compared with simulation results. The proposed system offers improved performance over conventional three level inverter in terms of THD.

Measuring Pattern Recognition from Decision Tree and Geometric Data Analysis of Industrial CR Images (산업용 CR영상의 기하학적 데이터 분석과 의사결정나무에 의한 측정 패턴인식)

  • Hwang, Jung-Won;Hwang, Jae-Ho
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.45 no.5
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    • pp.56-62
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    • 2008
  • This paper proposes the use of decision tree classification for the measuring pattern recognition from industrial Computed Radiography(CR) images used in nondestructive evaluation(NDE) of steel-tubes. It appears that NDE problems are naturally desired to have machine learning techniques identify patterns and their classification. The attributes of decision tree are taken from NDE test procedure. Geometric features, such as radiative angle, gradient and distance, are estimated from the analysis of input image data. These factors are used to make it easy and accurate to classify an input object to one of the pre-specified classes on decision tree. This algerian is to simplify the characterization of NDE results and to facilitate the determination of features. The experimental results verify the usefulness of proposed algorithm.

The Performance Improvement of CMA Adaptive Equalization in 16-QAM Signal using the Coordinate Reduction (Coordinate Reduction을 이용한 16-QAM 신호의 CMA 적응 등화 성능 개선)

  • Lim, Seung-Gag;Jeong, Young-Hwa
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.11 no.3
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    • pp.107-113
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    • 2011
  • This paper is concerned with the CR-CMA (Coordinate Reduction-Constant Modulus Algorithm) adaptive equalization algorithm using the coordinate reduction in order to improve the convergence characteristic and residual intersymbol interference which are used as the performance index for an adaptive equalizer. The equalizer is used to reduce the distortion caused by the intersymbol interference on the wireless and the wired band-limited channel that connect the transmitting system and receiving system. The CMA is widely known as the representative algorithm for equalization. In order to transmitting the mass information with a high speed through the channels, a fast convergence speed in the equalizer performance that is able to minimize overhead needed for equalization is acquired. In this paper, we introduce the new cost function to reduce the constellation of received signal at the input stage of a equalizer. It reduce the error at the steady equalization state. By the computer simulation, we confirmed that the proposed CR-CMA algorithm has the faster convergence speed and the smaller residual intersymbole interference than the conventional CMA.

Improve Stability of Military Infrared Image and Implement Zynq SoC (군사용 적외선 영상의 안정화 성능 개선 및 Zynq SoC 구현)

  • Choi, Hyun;Kim, Young-Min;Kang, Seok-Hoon;Cho, Joong-Hwee
    • IEMEK Journal of Embedded Systems and Applications
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    • v.13 no.1
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    • pp.17-24
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    • 2018
  • Military camera equipment has a problem that observability is inferior due to various shaking factors. In this paper, we propose an image stabilization algorithm considering performance and execution time to solve this problem and implemented it in Zynq SoC. We stabilized both the simple shaking in the fixed observation position and the sudden shaking in the moving observation position. The feature of the input image is extracted by the Sobel edge algorithm, the subblock with the large edge data is selected, and the motion vector, which is the compensation reference, is calculated through template matching using the 3-step search algorithm of the region of interest. In addition, the proposed algorithm can distinguish the shaking caused by the simple shaking and the movement by using the Kalman filter, and the stabilized image can be obtained by minimizing the loss of image information. To demonstrate the effectiveness of the proposed algorithm, experiments on various images were performed. In comparison, PSNR is improved in the range of 2.6725~3.1629 (dB) and image loss is reduced from 41% to 15%. On the other hand, we implemented the hardware-software integrated design using HLS of Xilinx SDSoC tool and confirmed that it operates at 32 fps on the Zynq board, and realized SoC that operates with real-time processing.

Optimization of $\mu$0 Algorithm for BDD Minimization Problem

  • Lee, Min-Na;Jo, Sang-Yeong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.2
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    • pp.82-90
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    • 2002
  • BDD have become widely used for various CAD applications because Boolean functions can be represented uniquely and compactly by using BDD. The size of the BDD representation for a function is very sensitive to the choice of orderings on the input variable. Therefore, it is very important to find a good variable ordering which minimize the size of the BDD. Since finding an optimal ordering is NP-complete, several heuristic algorithms have been proposed to find good variable orderings. In this paper, we propose a variable ordering algorithm, Faster-${\mu}$0, based on the ${\mu}$0(microcanonical optimization). In the Faster-${\mu}$0 algorithm, the initialization phase is replaced with a shifting phase to produce better solutions in a fast local search. We find values for algorithm parameters experimentally and the proposed algorithm has been experimented on well known benchmark circuits and shows superior performance compared to various existing algorithms.

Proposal and Performance Evaluation of A Scalable Scheduling Algorithm According to the Number of Parallel Processors (병렬 처리장치의 개수에 따른 스케줄링 알고리즘의 제안 및 성능평가)

  • Gyung-Leen Park;Sang Joon Lee;BongKyu Lee
    • Journal of Internet Computing and Services
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    • v.1 no.2
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    • pp.19-28
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    • 2000
  • The scheduling problem in parallel processing systems has been a challenging research issue for decades. The problem is defined as finding an optimal schedule which minimizes the parallel execution time of an application on a target multiprocessor system. Duplication Based Scheduling (DBS) is a relatively new approach for solving the problem. The DBS algorithms are capable of reducing communication overhead by duplicating remote parent tasks on local processors. Most of DBS algorithms assume an availability of the unlimited number of processors in the system. Since the assumption may net hold in practice, the paper proposes a new scalable DBS algorithm for a target system with limited number of processors. It Is shown that the proposed algorithm with N available processors generates the same schedule as that obtained by the algorithm with unlimited number of processors, where N is the number of input tasks. Also, the performance evaluation reveals that the proposed algorithm shows a graceful performance degradation as the number of available processors in the system is decreased.

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A Design of Hybrid Lossless Audio Coder (Hybrid 무손실 오디오 부호화기의 설계)

  • 박세형;신재호
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.41 no.6
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    • pp.253-260
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    • 2004
  • This paper proposes a novel algorithm for hybrid lossless audio coding, which employs an integer wavelet transform and a linear prediction model. The proposed algorithm divides the input signal into flames of a proper length, decorrelates the framed data using the integer wavelet transform and linear prediction and finally entropy-codes the frame data. In particular, the adaptive Golomb-Rice coding method used for the entropy coding selects an optimal option which gives the best compression efficiency. Since the proposed algorithm uses integer operations, it significantly improves the computation speed in comparison with an algorithm using real or floating-point operations. When the coding algorithm is implemented in hardware, the system complexity as well as the power consumption is remarkably reduced. Finally, because each frame is independently coded and is byte-aligned with respect to the frame header, it is convenient to move, search, and edit the coded, compressed data.

Sphere Decoding Algorithm and VLSI Implementation Using Two-Level Search (2 레벨 탐색을 이용한 스피어 디코딩 알고리즘과 VLSI 구현)

  • Huynh, Tronganh;Cho, Jong-Min;Kim, Jin-Sang;Cho, Won-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.104-110
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    • 2008
  • In this paper, a novel 2-level-search sphere decoding algorithm for multiple-input multiple-output (MIMO) detection and its VLSI implementation are presented. The proposed algorithm extends the search space by concurrently performing symbol detection on 2 level of the tree search. Therefore, the possibility of discarding good candidates can be avoided. Simulation results demonstrate the good performance of the proposed algorithm in terms of bit-error-rate (BER). From the proposed algorithm, an efficient very large scale integration (VLSI) architecture which incorporates low-complexity and fixed throughput features is proposed. The proposed architecture supports many modulation techniques such as BPSK, QPSK, 16-QAM and 64-QAM. The sorting block, which occupies a large portion of hardware utilization, is shared for different operating modes to reduce the area. The proposed hardware implementation results show the improvement in terms of area and BER performance compared with existing architectures.

Super-Resolution Algorithm Using Motion Estimation for Moving Vehicles (움직임 추정 기법을 이용한 움직이는 차량의 초고해상도 복원 알고리즘)

  • Kim, Seung-Hoon;Cho, Sang-Bock
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.49 no.4
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    • pp.23-31
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    • 2012
  • This paper proposes a motion estimation-based super resolution algorithm to restore input low-resolution images of large movement into a super-resolution image. It is difficult to find the sub-pixel motion estimation in images of large movement compared to typical experimental images. Also, it has disadvantage which have high computational complexity to find reference images and candidate images using general motion estimation method. In order to solve these problems for the traditional two-dimensional motion estimation using the proposed registration threshold that satisfy the conditions based on the reference image is determined. Candidate image with minimum weight among the best candidates for super resolution images, the restoration process to proceed with to find a new image registration algorithm is proposed. According to experimental results, the average PSNR of the proposed algorithm is 31.89dB and this is better than PSNR of traditional super-resolution algorithm and it also shows improvement of computational complexity.

Fast DOA Estimation Algorithm using Pseudo Covariance Matrix (근사 공분산 행렬을 이용한 빠른 입사각 추정 알고리듬)

  • 김정태;문성훈;한동석;조명제;김정구
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.40 no.1
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    • pp.15-23
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    • 2003
  • This paper proposes a fast direction of arrival (DOA) estimation algorithm that can rapidly estimate incidence angles of incoming signals using a pseudo covariance matrix. The conventional subspace DOA estimation methods such as MUSIC (multiple signal classification) algorithms need many sample signals to acquire covariance matrix of input signals. Thus, it is difficult to estimate the DOAs of signals because they cannot perform DOA estimation during receiving sample signals. Also if the D0As of signals are changing rapidly, conventional algorithms cannot estimate incidence angles of signals exactly. The proposed algorithm obtains bearing response and directional spectrum after acquiring pseudo covariance matrix of each snapshot. The incidence angles can be exactly estimated by using the bearing response and directional spectrum. The proposed DOA estimation algorithm uses only concurrent snapshot so as to obtain covariance matrix. Compared to conventional DOA estimation methods. The proposed algorithm has an advantage that can estimate DOA of signal rapidly.