• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.39-48
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• 1997

The fast redundancy identification is required to perform an efficient test pattern genration. Due to the reconvergent fanouts which make the dependency among objectives and the fault propagation blocking, there may exist redundnat faults in the cirucit. This paper presents the isomorphism identification and the pseudo dominator algorithms which are useful to identify redundant faults in combinational circuits. The isomorphism identification algorithm determines whether mandatory objectives required for fault detection cannot be simultaneously satisfied from primary input assignments or not using binary decision diagrma. The pseudo dominator algorithm determines whether faults propagation is possible or not by considering all paths at a given fanout node. Several experiments using ISCAS 85 benchmark circuits demonstrate the efficiency and practicability of the algorithms.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.366-373
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• 2016

This paper proposes a pre-processing algorithm to improve the coding efficiency of perceptual video coding. First, an input image is decomposed into multiple sub-bands through linear sub-band decomposition. Then, the sub-bands that have low visual sensitivity are suppressed by assigning small gains to them. Experimental results show that if the proposed algorithm is adopted for pre-processing in a High Efficiency Video Coding (HEVC) encoder, it can provide significant bit-saving effects of approximately 12% in low delay mode and 9.4% in random access mode.

• Journal of Communications and Networks
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• v.16 no.6
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• pp.620-626
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• 2014

In this paper, we propose a parallel collaborative sphere decoder with a scalable architecture promising quasi-maximum likelyhood performance with a relatively small amount of computational resources. This design offers a hardware-friendly algorithm using a modified node operation through fixing the variable complexity of the critical path caused by the sequential nature of the conventional sphere decoder (SD). It also reduces the computational complexity compared to the fixed-complexity sphere decoder (FSD) algorithm by tree pruning using collaboratively operated node operators. A Monte Carlo simulation shows that our proposed design can be implemented using only half the parallel operators compared to the approach using an ideal fully parallel scheme such as FSD, with only about a 7% increase of the normalized decoding time for MIMO dimensions of $16{\times}16$ with 16-QAM modulation.

• Journal of Internet Computing and Services
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• v.7 no.1
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• pp.49-57
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 12B-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array, This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We have designed the circuit with the VHDL coding, implemented with a FPGA of 50,000 gates.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.10
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• pp.38-49
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• 1996

In this paper, we propose a fast hierarchical image segmentation using mathematical morphology. The proposed segmentation method is composed of five basic steps; multi-thresholding, open-close by reconstructing, mode operation, marker extraction, and region decision. In the multi-thresholding, an input image is simplified by Lloyd clustering algorithm. The multi-thresholded image then is more simplified by open-close by reconstruction and mode operating. In the region decision, to which region each uncertainty pixel belongs finally is decided by a watershed algorithm. Experimental results show that the quality of the segmentation results by the proposed method is not inferior to that by the conventional method and the average times elapsed by the proposed method can be reduced by one tghird of those elapsed by the conventional method.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.885-886
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• 2006

The purpose of this study is to develop the optimal system(AAC device), which helps a person with a profound communication disorder to communicate with other people. Therefore, this system includes the user interface enhancement that is the user adaptation mode algorithm. The symbol is made with a text and an icon which is converted into Korean. The message contiol operates scanning and adjusts rate control of row-column scanning and linear scanning. This embedded system includes voice input/output and voice recording as well suggested method that could apply optimal device access algorithm from clinical environment. Therefore, we are experting that even the current system itself will be able to improve the life quality of people who need to communicate with the help of devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.520-527
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• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1847-1850
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• 2002

In this paper, MPLS Router module supporting Differentiated Service(Diffserv) for quality of Service (QoS) and High-speed switching is proposed and implemented. And we compare and analyze the proposed architecture with the conventional one in terms of CLR (Cell Loss Rate) and average delay. Switch is an extended system of Queue of each VOQ and PHB in the manner of Input Queuing for QoS. Algorithm, Priority-iSLIP is used for its scheduling algorithm. The proposed architecture is modeled in C++ and verified.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.4
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• pp.116-129
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• 1993

This paper proposes an on-line Recognition scheme of cursive Korean characters based on the DP matching and fuzzy concept. The proposed algorithm, invariant to rotation and size, reduces greatly the computational requirement of dynamic programming by matching phonemes rather than character patterns, where the angle difference and the ration of lengths between input and reference patterns are adopted as matching features. The correct matching of poorly written cursive characters becomes possible by introducing the fuzzy concept in representing the features of phonemes and the ralative position between adjacent phonemes. Computer simulation results are observed to show the effectiveness of the proposed algorithm.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.131-137
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• 1997

In this paper, we propose an efficient motion adaptive 3-dimensional (3D) video coding algorithm using 3D subband coding (3D-SBC) and lattice vector quantization (LVQ) for low bit rate. Instead of splitting input video sequences into the fixed number of subbands along the temporal axes, we decompose them into temporal subbands of variable size according to motions in frames. Each spatio-temporally splitted 7 subbands are partitioned by quadtree technique and coded with lattice vector quantization(LVQ). The simulation results show 0.1∼4.3dB gain over H.261 in peak signal to noise ratio (PSNR) at low bit rate(64Kbps).