• Journal of the Korean Institute of Intelligent Systems
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• v.25 no.4
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• pp.392-397
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• 2015

Society has been developed through analogue, digital, and smart era. Every technology is going through consistent changes and rapid developments. In this competitive society, R&D strategy establishment is significantly useful and helpful for improving technology competitiveness. A patent document includes technical and legal rights information such as title, abstract, description, claim, and patent classification code. From the patent document, a lot of people can understand and collect legal and technical information. This unique feature of patent can be quantitatively applied for technology analysis. This research paper proposes a methodology for extracting core technology and patents based on quantitative methods. Statistical analysis and social network analysis are applied to IPC codes in order to extract core technologies with active R&D and high centralities. Then, core patents are also extracted by analyzing citation and family information.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.6
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• pp.1-7
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• 2010

This paper presents a novel implementation on multimedia fingerprinting algorithm based on BCH (Bose-Chaudhuri-Hocquenghem) code. The evaluation is put in force the colluder detection to n-1. In the proposed algorit hm, the used collusion attacks adopt logical combinations (AND, OR and XOR) and average computing (Averaging). The fingerprinting code is generated as below step: 1. BIBD {7,4,1} code is generated with incidence matrix. 2. A new encoding method namely combines BIBD code with BCH code, these 2 kind codes are to be fingerprinting code by BCH encoding process. 3. The generated code in step 2, which would be fingerprinting code, that characteristic is similar BCH {15,7} code. 4. With the fingerprinting code in step 3, the collusion codebook is constructed for the colluder detection. Through an experiment, it confirmed that the ratio of colluder detection is 86.6% for AND collusion, 32.8% for OR collusion, 0% for XOR collusion and 66.4% for Averaging collusion respectively. And also, XOR collusion could not detect entirely colluder and on the other hand, AND and Averaging collusion could detect n-1 colluders and OR collusion could detect k colluders.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.1
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• pp.187-196
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• 2016

Android applications are inherently vulnerable to a repackaging attack such that malicious codes are easily inserted into an application and then resigned by the attacker. These days, it occurs often that such private or individual information is leaked. In principle, all Android applications are composed of user defined methods and APIs. As well as accessing to resources on platform, APIs play a role as a practical functional feature, and user defined methods play a role as a feature by using APIs. In this paper we propose a scheme to analyze sensitive APIs mostly used in malicious applications in terms of how malicious applications operate and which API they use. Based on the characteristics of target APIs, we accumulate the knowledge on such APIs using a machine learning scheme based on Naive Bayes algorithm. Resulting from the learned results, we are able to provide fine-grained numeric score on the degree of vulnerabilities of mobile applications. In doing so, we expect the proposed scheme will help mobile application developers identify the security level of applications in advance.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.5
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• pp.462-468
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• 2017

In this paper IoT/WSN(Internet of Things/Wireless Sensor Network) has been modeled with a random geometric graph. And a performance of the decentralized code for the efficient storage of data which is generated from WSN has been analyzed. WSN with n=100 or 200 has been modeled as a random geometric graph and has been simulated for their performance analysis. When the number of the total nodes of WSN is n=100 or 200, the successful decoding probability as decoding ratio ${\eta}$ depends more on the number of source nodes k rather than the number of nodes n. Especially, from the simulation results we can see that the successful decoding rate depends greatly on k value than n value and the successful decoding rate was above 70% when $${\eta}{\leq_-}2.0$$. We showed that the number of operations of BP(belief propagation) decoding scheme increased exponentially with k value from the simulation of the number of operations as a ${\eta}$. This is probably because the length of the LT code becomes longer as the number of source nodes increases and thus the decoding computation amount increases greatly.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.3 s.309
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• pp.9-16
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• 2006

Many image and video compression algorithms work by splitting the image into blocks and producing variable-length code bits for each block data. If variable-length code data are transmitted consecutively over error-prone channel without any error protection technique, the receiving decoder cannot decode the stream properly. So the standard image and video compression algorithms insert some redundant information into the stream to provide some protection against channel errors. One of redundancies is resynchronization marker, which enables the decoder to restart the decoding process from a known state in the event of transmission errors, but its usage should be restricted not to consume bandwidth too much. The Error Resilient Entropy Code(EREC) is well blown method which can regain synchronization without any redundant information. It can work with the overall prefix codes, which many image compression methods use. This paper proposes EREREC method to improve FEREC(Fast Error-Resilient Entropy Coding). It first calculates initial searching position according to bit lengths of consecutive blocks. Second, initial offset is decided using statistical distribution of long and short blocks, and initial offset can be adjusted to insure all offset sequence values can be used. The proposed EREREC algorithm can speed up the construction of FEREC slots, and can improve the compressed image quality in the event of transmission errors. The simulation result shows that the quality of transmitted image is enhanced about $0.3{\sim}3.5dB$ compared with the existing FEREC when random channel error happens.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.150-161
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• 2013

This paper presents a new system which produces high resolution 3D contents by capturing multiview images of an object using multiple cameras, and estimating geometric and texture information of the object from the captured images. Even though a variety of multiview image-based 3D reconstruction systems have been proposed, it was difficult to generate high resolution 3D contents because multiview image-based 3D reconstruction requires a large amount of memory and computation. In order to reduce computational complexity and memory size for 3D reconstruction, the proposed system predetermines the regions in input images where an object can exist to extract object boundaries fast. And for fast computation of a visual hull, the system represents silhouettes and 3D-2D projection/back-projection relations by chain codes and 1D homographies, respectively. The geometric data of the reconstructed object is compactly represented by a 3D segment-based data format which is called DoCube, and the 3D object is finally reconstructed after 3D mesh generation and texture mapping are performed. Experimental results show that the proposed system produces 3D object contents of $800{\times}800{\times}800$ resolution with a rate of 2.2 seconds per frame.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.37-47
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• 2008

Exploitation of address generation units which are typically provided in DSPs plays an important role in DSP code generation since that perform fast address computation in parallel to the central data path. Offset assignment is optimization of memory layout for program variables by taking advantage of the capabilities of address generation units, consists of memory layout generation and address pointer assignment steps. In this paper, we propose an effective address pointer assignment method to minimize the number of address calculation instructions in DSP code generation. The proposed approach reduces the time complexity of a conventional address pointer assignment algorithm with fixed memory layouts by using minimum cost-nodes breaking. In order to contract memory size and processing time, we employ a powerful pruning technique. Moreover our proposed approach improves the initial solution iteratively by changing the memory layout for each iteration because the memory layout affects the result of the address pointer assignment algorithm. We applied the proposed approach to about 3,000 sequences of the OffsetStone benchmarks to demonstrate the effectiveness of the our approach. Experimental results with benchmarks show an average improvement of 25.9% in the address codes over previous works.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.5
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• pp.1087-1097
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• 2017

As the penetration rate of smartphones increases, the number of malicious codes targeting smartphones is increasing. I 360 Security 's smartphone malware statistics show that malicious code increased 437 percent in the first quarter of 2016 compared to the fourth quarter of 2015. In particular, malicious applications, which are the main means of distributing malicious code on smartphones, are aimed at leakage of user information, data destruction, and money withdrawal. Often, it is operated by an API, which is an interface that allows you to control the functions provided by the operating system or programming language. In this paper, we propose a mechanism to detect malicious application based on the similarity of API pattern in normal application and malicious application by learning pattern of API in application derived from static analysis. In addition, we show a technique for improving the detection rate and detection rate for each label derived by using the corresponding mechanism for the sample data. In particular, in the case of the proposed mechanism, it is possible to detect when the API pattern of the new malicious application is similar to the previously learned patterns at a certain level. Future researches of various features of the application and applying them to this mechanism are expected to be able to detect new malicious applications of anti-malware system.

• The KIPS Transactions:PartD
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• v.11D no.2
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• pp.371-380
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• 2004

E-commerce is in wide use with the rapid advance of internet technology. The main component of an e-commerce application is a Web-based database application. Currently, it takes a lot of time in developing Web applications since developers should write codes manually or semi-automatically for user interface forms and query processing of an application. Therefore, the productivity increase of Web-based database applications has been demanded. In this paper, we introduce a software tool, which we call the WebSiteGen2, that automatically generates the forms that we used as user interfaces and the EJB/JSP components that process the query made through the forms for an application that needs a new database or uses an existing database. The WebSiteGen2 thus increases the productivity, reusability, expandibility, and portability of an application by automatically generating a 3-tier application based on component technology. Moreover, one user interface form that are generated by the WebSiteGen2 provides information on an interested entity as well as information on all the directly or indirectly related entities with the interested one. In this paper, we explain the functionality and implementation of the WebSiteGen2 and then show the merits by comparing the WebSiteGen2 to the other commercial Web application generators.