• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.2
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• pp.83-87
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• 2011

Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. Almost systems require that the clock length is required prior to scheduling, the best value of the clock can be found only after evaluating different schedules. In this study, we presents a scheduling method that works simultaneously with synthesis by selecting a clock from a chainable operation set. Our scheduling algorithm is based on list scheduling and executes chaining considering bit level delays based on selected clock period. Experimental results show that our method improves the performance by 18 percent.

• Journal of Communications and Networks
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• v.13 no.4
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• pp.377-384
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• 2011

Cooperative beamforming has previously been proven to be an efficient way to improve the cooperative diversity. This method generally requires all relay nodes to participate in beamforming, which can be seen as "all participate" cooperative beamforming. However, not all relay nodes have constructive impacts on the end-to-end bit error rate (BER) performance. Based on this observation, we propose a new cooperative scheme which only selects those "appropriate" relay nodes to perform cooperative beamforming. Such relay nodes can be simply determined with mean channel gains. Therefore, the selection complexity is significantly reduced as global instantaneous channel state information is not required. This scheme guarantees that energy is only allocated to the "appropriate" relay nodes, and hence provides superior diversity. We also prove that power allocation among source and selected relay nodes is a convex problem, and can be resolved with lower computational complexity. Simulation results demonstrate that our scheme achieves an essential improvement in terms of BER performance for both optimal and limited feedback scenarios, as well as high energy-efficiency for the energy-constrained networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.467-472
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• 2008

One of the maindisadvantages of Orthogonal Frequency Division Multiplexing (OFDM) is the Peak to Average Power Ratio (PAPR) problem. To reduce PAPR and improve the error performance of the OFDM signal over a fading channel, an OFDM system combining an Adaptive Symbol Selection Scheme (ASSS) and channel estimation can be used. Because of the side information of ASSS, however, the data rate decreases in the conventional ASSS OFDM system. In this letter, to overcome this impairment, we propose a technique to transmit side information by using pilot tones, and demonstrate that the proposed technique can give reasonable bit error rate (BER) performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.579-582
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• 2015

The Mean-Shift is a robustness algorithm that can be used for tracking the object using the similarity of histogram distributions of target model and target candidate. However, Mean-shift using hue information has disadvantage of tracking a wrong target when the target and background has similar hue distributions. We then propose a robust Mean-Shift tracking algorithm using new image that combined upper 4bit-planes in hue and saturation, respectively.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.7
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• pp.3156-3167
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• 2020

One drawback of polar codes is that they are not universal, that is, to achieve optimal performance, different polar codes are required for different kinds of channel. This paper proposes a polar code construction scheme for Nakagami-m fading channel. The scheme fully considers the characteristics of Nakagami-m fading channel, and uses the optimized Bhattacharyya parameter bounds. The constructed code is applied to an orthogonal frequency division multiplexing (OFDM) system over Nakagami-m fading channel to prove the performance of polar code. Simulation result shows the proposed codes can get excellent bit error rate (BER) performance with successive cancellation list (SCL) decoding. For example, the designed polar code with cyclic redundancy check (CRC) aided SCL (L = 8) decoding achieves 1.1dB of gain over LDPC at average BER about 10^-5 under 4-quadrature amplitude modulation (4QAM) while the code length is 1024, rate is 0.5.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.619-620
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• 2006

This paper presents a design of a 6-bit 2.704Gsamples/s D/A converter (DAC) for DS-CDMA UWB transceivers. The proposed DAC was designed with a current steering segmented 4+2 architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is -0.081 LSB and the measured differential nonlinearity (DNL) is -0.065 LSB. The DAC implemented in a 0.13um CMOS technology shows s spurious free dynamic range (SFDR) of 50dB from dc to Nyquist frequency. The prototype DAC consumes 28mW for a Nyquist sinusoidal output signal at a 2.704Gsamples/s. The chip has an active area of $0.76mm^2$.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.4
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• pp.1390-1405
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• 2014

This paper investigates optimal relay selection and power allocation under an aggregate power constraint for cooperative wireless sensor networks assisted by amplify-and-forward relay nodes. By considering both transmission power and circuit power consumptions, the received signal-to-noise ratio (SNR) at the destination node is calculated, based on which, a relay selection and power allocation scheme is developed. The core idea is to adaptively adjust the selected relays and their transmission power to maximize the received SNR according to the channel state information. The proposed scheme is derived by recasting the optimization problem into a three-layered problem-determining the number of relays to be activated, selecting the active relays, and performing power allocation among the selected relays. Monte Carlo simulation results demonstrate that the proposed scheme provides a higher received SNR and a lower bit error rate as compared to the average power allocation scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.49-54
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• 2007

As digital contents based on 3D graphics are increased, the requirement for low power 3D graphic hardware for mobile devices is increased. We design a transformation engine for mobile 3D graphic processor. We propose a simplified transformation engine for mobile 3D graphic processor. The area of the transformation engine is reduced by merging a mapping transformation unit into a projective transformation unit and by replacing a clipping unit with a selection unit. It consists of a viewing transformation unit a projective transformation unit a divide by w nit, and a selection unit. It can process 32 bit floating point format of the IEEE-754 standard or a reduced 24 bit floating point format. It has a pipelined architecture so that a vertex is processed every 4 cycles except for the initial latency. The RTL code is verified using an FPGA.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.1
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• pp.114-123
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• 2003

This paper proposes an efficient method for encoding the shape information of the object in the image. The polygonal approximation method is categorized into a loss coding method and is widely used for approximating object's shape information. The proposed method selects less number of vertices than IRM (iterated refinement method) or PVS (progressive vertex selection) when the maximum distortion is given, so reduces the bit-rates. The proposed method selects the vertices of a polygon with a simple and efficient method considering the rate-distortion sense. We construct the shape information coder, which shows the outstanding performance in the rate-distortion sense, based on the conventional progressive vertex selection method and the new vertex selection condition that we propose in this paper. Simulation results show that the proposed method has better performance than other conventional vertex selection methods in the tate-distortion sense.

• Journal of the Korea Society for Simulation
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• v.18 no.2
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• pp.9-17
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• 2009

A face database has contained a large amount of facial information data since face recognition was widely used. With the increase of facial information data, the face recognition based on distributed processing method has been noticed as a major topic. In existing studies, there were lack of discussion about the transferring method for large data. So, we proposed a fuzzy logic-based bit compression rate selection method for distributed face recognition. The proposed method selects an effective bit compression rate by fuzzy inference based on face recognition rate, processing time for recognition, and transferred bit length. And, we compared the facial recognition rate and the recognition time of the proposed method to those of facial information data with no compression and fixed bit compression rates. Experimental results demonstrates that the proposed method can reduce processing time for face recognition with a reasonable recognition rate.