• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.31-37
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• 1995

In this paper, we propose a programmable 16 bit DSP architecture using FIFO instruction memory. With this DSP architecture, System structure, BUS structure, instruction set ant and an assembler for system test are developed. The characteristic of this structure is that it simply fetches instructions not from RAM but from FIFO using shift operations. Accordingly, System can be designed regardless of RAM access time. One cycle is enough to execute an instruction, if instruction pipeline is operated. Another merit of this structure is that we can obtain the same effect as instruction pipelining without constructing a complex pipelined controller by decreasing the pipeline number.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.246-251
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• 2006

In this paper, we introduce an implementation method of the CBS (Cycle Base Simulator), which describes the operation of a DSP (Digital Signal Processor) at a pipeline cycle level. The CBS is coded with C++, and is verified by comparing the results from the CBS and HDL simulation of the DSP with the various test vectors and application programs. The CBS shows the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The developed CBS can be used in evaluating the performance of the target DSP before the RTL(Register Transfer Level) coding as well as a reference for the RTL level design.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.169-172
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.10
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• pp.337-342
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• 2015

We develop a new parallelization method for Sieve of Eratosthenes algorithm, which enhances both computation speed and energy efficiency. A pipeline scheduling is included for better load balancing after proper workload partitioning. They run on multicore CPUs with hybrid parallel programming model which uses both message passing and multithreading computation. Experimental results performed on both small scale clusters and a PC with a mobile processor show significant improvement in execution time and energy consumptions.

• 한국가시화정보학회:학술대회논문집
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• 2006.12a
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• pp.73-77
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• 2006

Flow rate measurement is one of the difficult problems in the industrial applications. Especially, flow rate in a partially filled pipeline is affected by many parameters such as water level, channel slop, etc. In the present study, prior to the development of a flowmeter, the flow characteristics has been investigated by particle image velocimetry (PIV) measurements. Three-dimensional velocity distributions were obtained from sectional measurements of velocity profiles according to the water level. As a result, it is found that there is no similarity in the velocity profile when the lateral position is changed. In addition, the maximum velocity does not always occur on the free surface. It depends on the water level. In the aspect of flow rate measurement, the previous calculus based upon point measurement techniques is proved to be inaccurate because of the lack of whole flow information.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1153-1156
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• 1998

We describe a design of a simple but efficient floatingpoint processing architecture expoiting concurrent execution of scalar instructions for high performance in general-purpose microprocessors. This architecture employs 3 stage pipeline asyncronously working with integer processing unit to regulate instruction flows between two arithmetic units.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.293-296
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• 2000

In this paper, we designed a 192-tap echo canceller for a modem using VHDL. To evaluate errors, we used adaptive algorithm. We adopted pipeline technique and realized delay-taps with RAMs. We simulated this design using Altera MAX+PLUS II.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.301-304
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• 2000

In this paper, we designed a 256-point FFT processor using VHDL. We adopted Radix-2$^2$SDC(Single-path Delay Commutator) architectures to reduce the number of complex multipliers. We confirmed the operation of the design through simulation using Altera MAX+PLUS II.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.687-690
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• 2005

H.264/AVC에서 압축 효율을 향상시키기 위해 사용된 entropy coding중에 CABAC(Context-based Adaptive Binary Arithmetic Coding)은 하드웨어 복잡도가 높고 bit-serial 과정에서 data dependancy가 존재하기 때문에 빠른 연산이 어렵다. 본 논문에서는 adaptive arithmetic encoder와 정규화 과정을 효율적으로 구성하여 각 입력 심벌이 정규화 과정의 반복횟수에 관계없이 고정된 cycle에 encoding이 되도록 하였다. 제안한 구조는 pipeline으로 구성하기 용이하며, 이 경우 매 cycle에 한 입력 심벌의 encoding이 가능하다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.9
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• pp.3583-3597
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• 2020

In this paper, a parallel deep learning model using a convolutional neural network and a dilated convolutional neural network is proposed to classify Alzheimer's disease with high accuracy in PET/CT images. The developed model consists of two pipelines, a conventional CNN pipeline, and a dilated convolution pipeline. An input image is sent through both pipelines, and at the end of both pipelines, extracted features are concatenated and used for classifying Alzheimer's disease. Complimentary abilities of both networks provide better overall accuracy than single conventional CNNs in the dataset. Moreover, instead of performing binary classification, the proposed model performs three-class classification being Alzheimer's disease, mild cognitive impairment, and normal control. Using the data received from Dong-a University, the model performs classification detecting Alzheimer's disease with an accuracy of up to 95.51%.