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Estimation and Comparison of Stem Volume for Larix kaempferi in South Korea using the Stem Volume Model (수간재적모델에 따른 일본잎갈나무의 수간재적 추정 및 비교)

  • Ko, Chi-Ung;Moon, Ga-Hyun;Yim, Jong-Su;Lee, Sun-Jeoung;Kim, Dong-Geon;Kang, Jin-Taek
    • Journal of Korean Society of Forest Science
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    • v.108 no.4
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    • pp.592-599
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    • 2019
  • This study aimed to develop an equation for estimating stem volume for Larix kaempferiin South Korea using independent variables, diameter at breast height (DBH), and height as being closely associated with stem volume. Analysis was conducted on the growth performance of 2,840 Larix kaempferi samples across South Korea after felling them and gleaning diameter data according to both stem height and stem analyses. In order to test the fitness of six different stem taper equations, empirical assessment was conducted for fitness index (FI), bias, mean, and absolute deviation (MAD), and coefficient variation (%CV). The two selectedmodels found to be optimal were the following: model one (V=a+bDBH2), established by employing DBH only; and model four (V=a+bDBH2H), established by utilizing DBH and height, respectively. The findings of non-linear regression indicated statistical significance (p < 0.05) in a and b, which were the coefficients for the intercepts and slopes of the models. The FI of the models ranged between 94% and 99%, and the bias was close to zero, while MAD ranged from 0.01 to 0.05, and %CV from 5.97 to 14.43, indicating a high level of fitness. Thus, using the suggested models, the basic information necessary for forest management was obtained, and an estimation of the stem volume was effected without delay soon after effecting DBH and height measurements.

The Design of 10-bit 200MS/s CMOS Parallel Pipeline A/D Converter (10-비트 200MS/s CMOS 병렬 파이프라인 아날로그/디지털 변환기의 설계)

  • Chung, Kang-Min
    • The KIPS Transactions:PartA
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    • v.11A no.2
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    • pp.195-202
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    • 2004
  • This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

Performance Improvement of an Energy Efficient Cluster Management Based on Autonomous Learning (자율학습기반의 에너지 효율적인 클러스터 관리에서의 성능 개선)

  • Cho, Sungchul;Chung, Kyusik
    • KIPS Transactions on Computer and Communication Systems
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    • v.4 no.11
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    • pp.369-382
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    • 2015
  • Energy aware server clusters aim to reduce power consumption at maximum while keeping QoS(quality of service) compared to energy non-aware server clusters. They adjust the power mode of each server in a fixed or variable time interval to activate only the minimum number of servers needed to handle current user requests. Previous studies on energy aware server cluster put efforts to reduce power consumption or heat dissipation, but they do not consider energy efficiency well. In this paper, we propose an energy efficient cluster management method to improve not only performance per watt but also QoS of the existing server power mode control method based on autonomous learning. Our proposed method is to adjust server power mode based on a hybrid approach of autonomous learning method with multi level thresholds and power consumption prediction method. Autonomous learning method with multi level thresholds is applied under normal load situation whereas power consumption prediction method is applied under abnormal load situation. The decision on whether current load is normal or abnormal depends on the ratio of the number of current user requests over the average number of user requests during recent past few minutes. Also, a dynamic shutdown method is additionally applied to shorten the time delay to make servers off. We performed experiments with a cluster of 16 servers using three different kinds of load patterns. The multi-threshold based learning method with prediction and dynamic shutdown shows the best result in terms of normalized QoS and performance per watt (valid responses). For banking load pattern, real load pattern, and virtual load pattern, the numbers of good response per watt in the proposed method increase by 1.66%, 2.9% and 3.84%, respectively, whereas QoS in the proposed method increase by 0.45%, 1.33% and 8.82%, respectively, compared to those in the existing autonomous learning method with single level threshold.

Long-term Monitoring System for Ship's Engine Performance Analysis Based on the Web (선박엔진성능분석용 웹기반 장기모니터링시스템 구현)

  • Kwon, Hyuk-Joo;Yang, Hyun-Suk;Kim, Min-Kwon;Lee, Sung-Geun
    • Journal of Advanced Marine Engineering and Technology
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    • v.39 no.4
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    • pp.483-488
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    • 2015
  • This paper implements a long-term monitoring system (LMS) for ship's engine performance analysis (SEPA) based on the web, for the purpose of the communication speed and engine maintenance. This system is composed of a simulator, monitoring module with a multi channel A/D converter, monitoring computer, network attached storage (NAS), RS485 serial and wireless internet communication system. The existing products monitor the information transmitted from pressure sensors installed in the upper parts of each of engines in the local or web computer, but have a delay in the communication speed and errors in long-term monitoring due to the large volume of sampling pressure data. To improve these problems, the monitoring computer saves the sampling pressure data received from the pressure sensors in NAS, monitors the long-term sampling data generated by the sectional down sampling method on a local computer, and transmits them to the web for long-term monitoring. Because this method has one tenth of the original sampling data, it will use memory with small capacity, save communication cost, monitor the long-term sampling data for 30 days, and as a result, make a great contribution to engine maintenance.

A Design Solution for a Railway Switch Monitoring System (분기기 진단 시스템 설계에 관한 연구)

  • Choo, Eun-Sang;Kim, Min-Seong;Yoo, Heung-Yeol;Mo, Choong-Seon;Son, Eui-Sik;Park, Seongguen;Lee, Jong-Woo
    • Journal of the Korean Society for Railway
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    • v.18 no.5
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    • pp.439-446
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    • 2015
  • The turnout system, which determines the direction of the train, is not only a key system but also a vulnerable system. Failure of this system may lead to a delay of the train or even casualties. In this light, it is necessary to precisely the conditions of the turnout system. Currently, ROADMASTER of Germany is used as a diagnostic system in Korea. However, a new diagnostic system should be developed for optimized operation of the turnout system with maintenance that is suitable for the Korean railway environment. In this paper, a Fault Tree Analysis for the representative faults of the turnout system is conducted and physical quantities, which can be the cause of the fault, are classified according to the component and function. Also, the measuring factors for the monitoring are derived and a decision making theory is suggested. On the basis of the results, we propose a new turnout diagnostic system that can provide more driverse and precise information than the conventional system.

An Efficient CPLD Technology Mapping considering Area under Time Constraint (시간 제약 조건하에서 면적을 고려한 효율적인 CPLD 기술 매핑)

  • Kim, Jae-Jin;Kim, Hui-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.1
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    • pp.79-85
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    • 2001
  • In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

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Performance Analysis of the Gated Service Scheduling for Ethernet PON (Ethernet PON을 위한 Gated Service 스케줄링의 성능분석)

  • 신지혜;이재용;김병철
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.7
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    • pp.31-40
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    • 2004
  • In this paper, we analyze mathematically the performance of the gated service scheduling in the Interleaved Polling with Adaptive Cycle Time(IPACT) was proposed to control upstream traffic for Gigabit Ethernet-PONs. In the analysis, we model EPON MAC protocol as a polling system and use mean value analysis. We divide arrival rate λ into three regions and analyze each region accordingly In the first region in which λ value is very small, there are very few ONUs' data to be transmitted. In the second region in which λ has reasonably large value, ONUs have enough data for continuous transmission. In the third region, ONUs' buffers are always saturated with data since λ value is very large. We obtain average packet delay, average Queue size, average cycle time of the gated service. We compare analysis results with simulation to verify the accuracy of the mathematical analysis. Simulation requires much time and effort to evaluate the performance of EPONs. On the other hand, mathematical analysis can be widely used in the design of EPON systems because system designers can obtain various performance results rapidly. We can design appropriate EPON systems for varioustraffic property by adjusting control parameters.

The Design of A Fast Two′s Complement Adder with Redundant Binary Arithmetic (RB 연산을 이용한 고속 2의 보수 덧셈기의 설계)

  • Lee, Tae-Uk;Jo, Sang-Bok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.5
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    • pp.55-65
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    • 2000
  • In this paper a new architecture of 24-bit two's complement adder is designed by using RB(Redundant Binary) arithmetic which has the advantage of CPF(Carry-Propagation-Free). A MPPL(Modified PPL) XOR/XNOR gate is applied to improve a TC2RB(Two's Complement to RB SUM converter) speed and to reduce the number of transistors, and we proposed two types adder which used a fast RB2TC(RB SUM to Two's Complement converter). The property of two types adder is followings. The improvement of TYPE 1 adder speed is archived through the use of VGS(Variable Group Select) method and TYPE 2 adder is through the use of a 64-bit GCG(Group Change bit Generator) circuit and a 8-bit TYPE 1 adder. For 64-bit, TYPE 1 adder can be expected speed improvement of 23.5%, 25.7% comparing with the CLA and CSA, and TYPE 2 adder can be expected 41.2%, 45.9% respectively. The propagation delay of designed 24-bit TYPE 1 adder is 1.4ns and TYPE 2 adder is 1.2ns. The implementation is highly regular with repeated modules and is very well suited for microprocessor systems and fast DSP units.

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The Cell Resequencing Buffer for the Cell Sequence Integrity Guarantee for the Cyclic Banyan Network (사이클릭 벤얀 망의 셀 순서 무결성 보장을 위한 셀 재배열 버퍼)

  • 박재현
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.9
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    • pp.73-80
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    • 2004
  • In this paper, we present the cell resequencing buffer to solve the cell sequence integrity problem of the Cyclic banyan network that is a high-performance fault-tolerant cell switch. By offering multiple paths between input ports and output ports, using the deflection self-routing, the Cyclic banyan switch offer high reliability, and it also solves congestion problem for the internal links of the switch. By the way, these multiple paths can be different lengths for each other. Therefore, the cells departing from an identical source port and arriving at an identical destination port can reach to the output port as the order that is different from the order arriving at input port. The proposed cell resequencing buffer is a hardware sliding window mechanism. to solve such cell sequence integrity problem. To calculate the size of sliding window that cause the prime cost of the presented device, we analyzed the distribution of the cell delay through the simulation analyses under traffic load that have a nonuniform address distribution that express tile Property of traffic of the Internet. Through these analyses, we found out that we can make a cell resequencing buffer by which the cell sequence integrity is to be secured, by using a, few of ordinary memory and control logic. The cell resequencing buffer presented in this paper can be used for other multiple paths switching networks.

Risk Factors for Allergic Diseases in School-Aged Children (알레르기 질환을 가진 초등학교 고학년의 식생활·환경적 요인 및 성장과의 관련성 분석)

  • Min, Seonae;Cho, Mijin;Park, Kyong
    • Journal of the Korean Society of Food Science and Nutrition
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    • v.42 no.9
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    • pp.1387-1394
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    • 2013
  • Allergies are one of the most common chronic diseases during childhood. While the prevalence of allergic disease in children is increasing dramatically, few studies have evaluated the risk and preventive factors related to this health condition, especially in South Korea. The purpose of this case-control study was to evaluate independent determinants of allergic disease, and to examine whether it is associated with growth and other health conditions in childhood. The current study included 209 cases and 311 age and sex-matched controls (fifth and sixth graders) residing in Daegu, South Korea. Environmental data was collected, including child and family histories of allergies, birth information, and reaction to weaning foods during infancy. In addition, current dietary habits (assessed by 2 day-24 hr food records), health conditions, and anthropometric data were obtained through questionnaires and student health check-ups at the school. Based on chi-square tests, cases had a significantly higher prevalence of having a disease at birth, an allergic reaction to weaning foods, frequent hospital visits, and frequent experiences of the common cold and digestive diseases. In addition, significantly more mothers had a higher education in the cases compared to controls. Based on multivariable conditional logistic regression analysis, factors significantly associated with greater odds for having allergies were parental (OR=21.42) and fraternal (OR=14.40) histories of allergies. The anthropometric measures showed that cases tended to be shorter in height and lighter in weight than the controls, but these differences were not statistically significant. These findings may indicate that current nutrient intakes may not be the only critical factor associated with delayed growth delay in the allergic group. A well-planned, large cohort study is warranted to confirm our findings in the future.