• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.567-570
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• 1989

A constant V/F control system of voltage contrlled PWM inverter has a unstable operation of the low- speed and the light-load. In this paper, the authors propose stability control with idealized operation of induction motor by the neglect of primary leakage inductance and resistance. Also ldealized operation system is adopted voltage error, feed back impedance circuit, and increasing resistance from dead time of switching is compensated by the soft ware with u-processors. The proposed simulation of the idealized control method is proved at the low-speed operation for three phase induction motor.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.10
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• pp.522-527
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• 2003

This paper proposes a new speed and flux estimation method which has the robustness against the variation of the electrical parameters of the motor and the superiority in the dynamic characteristics. In the proposed method, the stator currents and the rotor fluxes are observed on the stationary reference frame using the sliding mode concept. And the rotor speed is estimated using the current estimation errors and the observed rotor fluxes based on the Lyapunov stability theory. Also a design method of the observer gain is proposed to minimize the effect of the speed estimation error on the rotor flux observation. The experimental results are shown to verify that the proposed method shows the excellent performances under the variations of motor resistance and inductance.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.8
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• pp.1217-1223
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• 2015

In this paper, we study the problem of torque ripple minimization in Brushless DC Motors (BLDC) and proposes a disturbance observer (DOB) based controller in order to efficiently reduce the torque ripple. In the DOB based control system, an equivalent disturbance (plant disturbance and effect of modelling error) is cancelled by its estimate. When the DOB controller is applied to BLDC motors, the effect of inverter switching is considered as an equivalent disturbance and to be cancelled by the DOB controller. Through computer simulations, it is shown that the performance of the proposed DOB controller is superior to that of the conventional PI controller. In the case where the numerical values of resistance and inductance are not known exactly, it is shown that the proposed DOB controller achieves better performance than the PI controller.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.6
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• pp.589-595
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• 2007

This paper presents a new method on controller design of brushless dc motors. In such drives the current ripples are generated by motor inductance in stator windings and the back EMF. To suppress the current ripples the current controller is generally used. To minimize the size and the cost of the drives it is desirable to control motors without the current controller and the current sensing circuits. To estimate the motor CUlTent it is modeled by a neural network that is contigured as an output-error dynamic system. The identified model is essentially a one step ahead prediction structure in which past inputs and outputs are used to calculate the current output. Using the model, a state feedback controller to compensate the effects of disturbance has been designed. The controller is implemented by a 16-bit microprocessor and the effectiveness of the proposed control method is verified through experiments.

• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.1138-1141
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• 2003

This paper proposes a new speed and flux estimation method which has the robustness against the variation of the electrical parameters of the motor and the superiority in the dynamic characteristics compared with the conventional sensorless schemes. In the proposed method, the stator currents and the rotor fluxes are observed on the stationary reference frame using the sliding mode concept. And the rotor speed is estimated using the current estimation errors and the observed rotor fluxes based on the Lyapunov stability theory. Also a design method of the observer gain is proposed to minimize the effect of the speed estimation error on the rotor flux observation. The experimental results verified that the proposed method shows more robust and improved performances than the previous estimation method under the variations of motor resistance and inductance.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.1
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• pp.40-49
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• 2008

Interior permanent magnet synchronous motor(IPMSM) has become a popular choice in electric vehicle applications and so of due to their excellent power to weight ratio. To obtain maximum efficiency in these applications, this paper proposes the neural network control method. The controllable electrical loss which consists of the copper loss and the iron loss can be minimized by the error back propagation algorithm(EBPA) of neural network. The minimization of loss is possible to realize eHciency optimization control for the IPMSM drive. This paper proposes high performance and robust control through a real time calculation of parameter variation such as variation of back emf constant, armature resistance and d-axis inductance about the motor operation. Proposed algorithm is applied IPMSM drive system, prove validity through analysis operating characteristics con011ed by efficiency optimization control.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.13-26
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• 1999

This paper presents a metric that can guide to optimal circuit models for interconnects among various models, given interconnect parameters and operating environment. To get this goal, we categorize interconnects into RC~c1ass and RLC-c1ass model domains based on the quantitative modeling error analysis using total resistance, inductance and capacitance of interconnects as well as operating frequency. RC~c1ass circuit models, which include most on~chip interconnects, can be efficiently analyzed by using the model~order reduction techniques. RLC-c1ass circuit models are constructed using one of three candidates, ILC(Iterative Ladder Circuit) macromodels, MC(Method of Characteristics) macromodels, and state-based convolution method, the selection process of which is based upon the allowable modeling error and electrical parameters of interconnects. We propose the model domain diagram leading to optimal circuit models and the division of model domains has been achieved considering the simulation cost of macromodels under the environmental assumption of the general purpose circuit simulator such as SPICE. The macromodeling method presented in this paper keeps the passivity of the original interconnects and accordingly guarantees the unconditional stability of circuit models.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.909-914
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• 2008

A coupling capacitor voltage transformer(CCVT) is used in an extra or ultra high voltage system to obtain the standard low voltage signal for protection. To avoid the phase angle error between the primary and secondary voltages, a tuning reactor is connected between a capacitor and a voltage transformer. The inductance of the reactor is designed based on the power system frequency. If a fault occurs on the power system, the secondary voltage of the CCVT contains some errors due to a dc offset component and harmonic components resulting from the fault. The errors become severe in the case of a close-in fault. This paper proposes an algorithm for compensating the secondary voltage of a CCVT in the time-domain. From the measured secondary voltage of the CCVT, the secondary and primary currents are obtained; then the voltage across the capacitor and the inductor is calculated and then added to the measured secondary voltage to obtain the correct primary voltage. Test results indicate that the proposed algorithm can compensate the distorted secondary voltage of the CCVT irrespective of the fault distance, the fault inception angle, and the burden of the CCVT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.67-75
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• 2004

This paper presents a buffer insertion method for RLC-class interconnect structured as a sin91e line or a tree. First, a closed form expression for the interconnect delay of a CMOS buffer driving single RLC line is represented. This expression has been derived by the n-th power law for deep submicrometer technology and occurs to be within 9 percentage of maximal relative error in accuracy compared with the results of HSPICE simulation for various RLC loads. This paper proposes a closed form expression based on this for the buffer insertion of single RLC lines and the buffer sizing algorithms for RLC tree interconnects to optimize path delays. The proposed buffer insertion algorithms are applied to insert buffers for several interconnect trees with a 0.25${\mu}{\textrm}{m}$ CMOS technology and the results are compared against those of HSPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.77-83
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• 2004

Cross-talk noise which can occur between on-chip interconnects is significant factor which influence signal integrity. Therefore, this paper presents an analytical method for estimating maximum cross-talk noise. We consider inductance effect of interconnects and use arbitary ramp inputs to estimate noise magnitude exactly. Also, we have used a virtual source for the easy of analytically caculating maximum cross-talk noise from complex cross-talk noise model. The accuracy of the has been shown that be within 4.3 percent maximum relative error compared with the results of HSPICE simulation. Hence, this study can be utilized in various CAD tools for guaranteeing signal integrity.