• 한국전자통신학회논문지
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• 제18권5호
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• pp.777-784
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• 2023

감지 증폭기는 메모리 설계에 필수적인 주변 회로로서, 작은 차동 입력 신호를 감지하여 디지털 신호로 증폭하기 위해 사용된다. 본 논문에서는 인 메모리 컴퓨팅 회로에서 활용 가능한 고속 감지 증폭기를 제안하였다. 제안하는 회로는 추가적인 방전 경로를 제공하는 트랜지스터 Mtail을 통해 감지 지연 시간을 감소시키고, m-GDI(:modified Gate Diffusion Input)를 적용하여 감지 증폭기의 회로 성능을 개선하였다. 기존 구조와 비교했을 때 감지 지연 시간은 16.82% 감소하였으며, PDP(: Power Delay Product)는 17.23%, EDP(: Energy Delay Product)은 31.1%가 감소하는 결과를 보였다. 제안하는 회로는 TSMC의 65nm CMOS 공정을 사용하여 구현하였으며 SPECTRE 시뮬레이션을 통해 본 연구의 타당성을 검증하였다.

• 대한전기학회논문지
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• 제32권12호
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• pp.435-440
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• 1983

The methods of forming the bus impedance matrix, which is mainly employed in fault analysis of power system, can be generally classified in catagories, (1) the one being the inverse matrix of bus admittance matrix, and (2) the other the bus impedance matrix succesive formation method by particular algorithms. The former method is theouetically elegant, but the formation and inverse of complex bus admittance matrix for large power system requires too much amounts of computer memory space and computing time. The latter method also requires too much memory space. Therefore, in this paper, an algorithm and computer program is introduced for the formation of a sparse bus impedance matrix which generates only the matching terms of the admittance matrix. So, this method can reduce the computer memory and computing time, and can be applied to fault analysis of large power system by small digital computer.

• Journal of the Korean Data and Information Science Society
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• 제26권5호
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• pp.1035-1045
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• 2015

최근 빅데이터 분야에서 데이터를 메모리에 적재 후 빠르게 처리하는 인메모리 컴퓨팅 기술이 새롭게 부각되고 있다. 인메모리 컴퓨팅 기술은 과거 대용량 메모리와 다중 프로세서를 탑재한 고성능서버에 적용 가능하였지만, 점차 일반 컴퓨터를 초고속 네트워크로 연결하여 분산 병렬처리가 가능한 구조로 변화하고 있다. 본 논문은 In-memory data grid (IMDG) 기술을 택시 애플리케이션에 접목하여 기존의 데이터베이스의 변경 없이 성능을 향상시키는 기법을 제안한다. IMDG 기술을 적용한 경우 기존의 데이터베이스 기반의 웹서비스에 비해 처리속도와 처리량이 평균 6~9배정도 증가하며, 또한 부하량에 따른 처리량 변화의 폭이 매우 작음을 확인 하였다.

• International Journal of Computer Science & Network Security
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• 제22권4호
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• pp.89-100
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• 2022

With the advancement in the Internet of things Technology (IoT) cloud computing, billions of physical devices have been interconnected for sharing and collecting data in different applications. Despite many advancements, some latency - specific application in the real world is not feasible due to existing constraints of IoT devices and distance between cloud and IoT devices. In order to address issues of latency sensitive applications, fog computing has been developed that involves the availability of computing and storage resources at the edge of the network near the IoT devices. However, fog computing suffers from many limitations such as heterogeneity, storage capabilities, processing capability, memory limitations etc. Therefore, it requires an adequate task scheduling method for utilizing computing resources optimally at the fog layer. This work presents a comprehensive review of different task scheduling methods in fog computing. It analyses different task scheduling methods developed for a fog computing environment in multiple dimensions and compares them to highlight the advantages and disadvantages of methods. Finally, it presents promising research directions for fellow researchers in the fog computing environment.

• International journal of advanced smart convergence
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• 제12권4호
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• pp.164-170
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• 2023

With the recent advances in AI (artificial intelligence) and HPC (high-performance computing) technologies, deep learning is proliferated in various domains of the 4th industrial revolution. As the workload volume of deep learning increasingly grows, analyzing the memory reference characteristics becomes important. In this article, we analyze the memory reference traces of deep learning workloads in comparison with traditional workloads specially focusing on read and write operations. Based on our analysis, we observe some unique characteristics of deep learning memory references that are quite different from traditional workloads. First, when comparing instruction and data references, instruction reference accounts for a little portion in deep learning workloads. Second, when comparing read and write, write reference accounts for a majority of memory references, which is also different from traditional workloads. Third, although write references are dominant, it exhibits low reference skewness compared to traditional workloads. Specifically, the skew factor of write references is small compared to traditional workloads. We expect that the analysis performed in this article will be helpful in efficiently designing memory management systems for deep learning workloads.

• Journal of Information Technology Applications and Management
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• 제12권4호
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• pp.59-70
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• 2005

Flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional transaction management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. in order to achieve this goal, we devise a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient transaction processing. F2Pl improves transaction performance by allowing multi version reads and efficiently handling slow flash write/erase operation in lock management process. We also propose a simulation model to show the performance of F2PL. Based on the results of the performance evaluation, we conclude that F2PL scheme outperforms the traditional scheme.

• Journal of Information Processing Systems
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• 제18권1호
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• pp.159-172
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• 2022

The role of the interconnect network, which connects computing nodes to each other, is important in high-performance computing (HPC) systems. In recent years, the peripheral component interconnect express (PCIe) has become a promising interface as an interconnection network for high-performance and cost-effective HPC systems having the features of non-transparent bridge (NTB) technologies. OpenSHMEM is a programming model for distributed shared memory that supports a partitioned global address space (PGAS). Currently, little work has been done to develop the OpenSHMEM library for PCIe-interconnected HPC systems. This paper introduces a prototype implementation of the OpenSHMEM library through a switchless interconnect network using PCIe NTB to provide a PGAS programming model. In particular, multi-interrupt, multi-thread-based data transfer over the OpenSHMEM shared memory model is applied at the implementation level to reduce the latency and increase the throughput of the switchless ring network system. The implemented OpenSHMEM programming model over the PCIe NTB switchless interconnection network provides a feasible, cost-effective HPC system with a PGAS programming model.

• 정보학연구
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• 제10권4호
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• pp.41-56
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• 2007

In Digital Computing Environment, volatile information such as register, cache memory, and network information are hard to make certain of a real-time collection because such volatile information are easily modified or disappeared. Thus, a collection of volatile information is one of important step for computer forensics system on ubiquitous computing. In this paper, we propose a volatile information collection module, which collects variable volatile information of server system based on memory mapping in real-time.

• 한국콘텐츠학회:학술대회논문집
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• 한국콘텐츠학회 2008년도 춘계 종합학술대회 논문집
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• pp.507-513
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• 2008

디지털 콘텐츠 컴퓨팅 환경에서 서비스를 제공하는 서버시스템의 레지스터, 캐시메모리, 네트워크 정보 등의 휘발성 정보는 침해사고 이후 시간의 경과나 외부의 조작으로 사라지거나 변조되기 쉽기 때문에 실시간으로 확보하는 것이 중요하다. 본 논문에서는 디지털 콘텐츠 컴퓨팅 환경의 서버 시스템에서 휘발성 정보를 메모리를 기반으로 수집하는 기법을 활용하여 동작 중인 서버에서 위급상황이 발생할 시 필요한 정보를 실시간으로 수집할 수 있는 휘발성 정보 수집 모듈을 제안한다.

• 한국컴퓨터정보학회논문지
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• 제22권4호
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• pp.17-24
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• 2017

In this paper, we propose an efficient dynamic workload balancing strategy which improves the performance of high-performance computing system. The key idea of this dynamic workload balancing strategy is to minimize execution time of each job and to maximize the system throughput by effectively using system resource such as CPU, memory. Also, this strategy dynamically allocates job by considering demanded memory size of executing job and workload status of each node. If an overload node occurs due to allocated job, the proposed scheme migrates job, executing in overload nodes, to another free nodes and reduces the waiting time and execution time of job by balancing workload of each node. Through simulation, we show that the proposed dynamic workload balancing strategy based on CPU, memory improves the performance of high-performance computing system compared to previous strategies.