• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.10
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• pp.940-947
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• 2007

For the performance upgrade of a supersonic jet fighter, the processor and FLCC(Flight Control Computer) Architecture were upgraded from a baseline FLCC. Prior to the hardware implementation phase, the exact CPU throughput estimation is necessary. For this purpose, an experimental method for new FLCC throughput estimation was introduced in this study.　While baseline FLCC operating, the CPU address bus was collected with logic analyzer, and then decoded to get the exact access times to each memory-memory and the number of program Instruction branches. Based on these data, a throughput test in CPU demo-board of the new FLCC configuration was performed. From test results, the CPU-Memory architecture was design-changed before FLCC hardware implementation phase. To check the flight stability degradation due to power-interrupt problem due to CPU-Memory architecture change, the piloted HILS (Hardware-In-the Loop Simulator) test was conducted.

• Environmental Analysis Health and Toxicology
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• v.21 no.2 s.53
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• pp.197-208
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• 2006

The hazards of chemicals can be classified using classification criteria that are based on physical, chemical and ecotoxicological endpoints. These criteria may be developed be iteratively, based on scientific or regulatory processes. A number of national and international schemes have been developed over the past 50 years, and some, such as the UN Dangerous Goods system or the EC system for hazardous substances, are in widespread use. However, the unnecessarily complicated multiplicity of existing hazard classifications created much unnecessary confusion at the user level, and a recommendation was made at the 1992 Rio Earth summit to develop a globally harmonized chemical hazard classification and compatible labelling system, including material safety data sheets and easily understandable symbols, that could be used for manufacture, transport, use and disposal of chemical substances. This became the globally harmonized system for the Classification and Labelling of Chemicals (GHS). The developmental phase of the GHS is largely complete. Consistent criteria for categorizing chemicals according to their toxic, physical, chemical and ecological hazards are now available. Consistent hazard communication tools such as labelling and material safety data sheets are also close to finalizations. The next phase is implementation of the GHS. The Intergovernmental Forum for Chemical Safety recommends that all countries implement the GHS as soon as possible with a view to have the system fully operational by 2008. When the GHS is in place, the world will finally have one system for classification of chemical hazards.

• Journal of the Korea Society of Computer and Information
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• v.16 no.2
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• pp.47-53
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• 2011

The detection process of defective tags in most of Korean domestic RFID manufacturing companies is treated by on-hand processing after the job of chip bonding, so it has been requested to reduce the time and cost for manufacturing of RFID tags. Therefore, in this paper, we implement the system to perform the detection of defective tags after the process of chip bonding, and so provide the basis of software to establish the foundation of automation system for the detection of defected RFID tags which is requested in the related Korean domestic industrial field. We have developed the system by using UML in modeling phase and JAVA in implementation phase to reduce the cost of development of program and make it easy to maintain. The developed system in this paper shows the very enhanced performance in processing speed and perfect detection rate of defective tags, comparing to the method of on-hand processing.

• Journal of the Society of Disaster Information
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• v.15 no.4
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• pp.493-501
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• 2019

Purpose: The purpose of this study is to prevent construction safety accidents, and the design safety systems were reviewed. This paper aims to establish as an effective system by looking at the implementation procedures and contents of the design safety review system. Method: We reviewed the purpose and content of the law, accident statistics, etc. for the study. In addition, we looked at the implementation plans for actual construction sites using the 'design safety' assessment process as defined by the Act. Results: We divided it into the data review phase, the risk factor elicitation and alternative setup phase, and the design safety assessment report preparation stage. Conclusion: it is necessary to derive risk factors that take into account the diversity of construction sites. However, the effectiveness of other reports is questioned as they are often copied and written. Therefore, it is necessary to strengthen external verification procedures attended by construction safety experts.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.5
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• pp.568-573
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• 2019

Modern Radars are evolving into MFRs which can search multiple targets simultaneously and then track them. Additionally they should be able to avoid some external jamming signals. Applying to these MFRs, Antennas should be able to perform DBF including to not only real-time beam steering but also multi-beam forming simultaneously. And they can cancel the beam at the specific direction. In this paper, we describe the implementation of sub-array type antenna hardware which can be applying DBF. Also we propose the modified amplitude aperture distribution for suppressing the side lobe level and explain the sub-array receiver design with amplitude tapering. It consists in making the amplitude weighting in 2 steps. In order to compare two weighting cases, we investigate the G/T performance for the array antenna. At the conclusion, we make a comparative study for the dynamic range of every sub-array receiver and present the hardware implementation that is more advantageous for sub-array alignment and calibration in DBF.

• Journal of IKEEE
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• v.24 no.4
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• pp.1028-1033
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• 2020

The existing in-band interference reduction method recommends the physical separation distance between wireless devices and interference signals, and the interference can be suppressed through the separation distance. If the in-band interference signals can be reduced in a wireless device, a margin can be given to the physical separation distance. Since there is an effect of extending the receiver dynamic range of receivers, it is highly useful for interference reduction and improvement method. In this paper, the structure of an in-band analog IRM(Interference Reduction Module) is proposed and the design and implementation of the proposed analog IRM are described. To design an analog IRM, the interference reduction performance according to the delay mismatch, phase error and the number of delay lines that affect the performance of the analog IRM was simulated. The proposed analog IRM composed of 16 delay lines was implemented and the implemented IRM has the interference reduction performance of about 10dB for a 5G(NR-FR1-TM-1.1) signal having a 40MHz bandwidth at a center frequency of 3.32GHz. The analog IRM proposed in this paper can be used as an in-band interference canceller.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.7
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• pp.955-961
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• 2021

In modern warfare, the importance of electronic warfare, which carries out a mission that using radio wave to find out enemy information or to protect ally information, has increased. Radar jamming technique is one of the most representative techniques of EA(Electronic Attack), it disturbs and deceives enemy radar system in order to secure ally location information. Velocity deception jamming technique, which is one of the radar jamming techniques, generally operate against pulse-doppler radar which use doppler effect in order to track target's velocity and location. Velocity Deception Jamming Technique can be implemented using DRFM(Digital Radio Frequency Memory) that performs Frequency Modulation. In this paper, I describe implementation method of VGPO/VGPI(Velocity Gate Pull-Off/Pull-In) velocity deception jamming technique using phase-sampled DRFM, and verify the operation of VGPO/VGPI velocity deception jamming technique with board test under signal injection condition.

• Educational Technology International
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• v.7 no.2
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• pp.93-106
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• 2006

The knowledge-based society increasingly demands professionals possessing essential knowledge, and the ability to use this knowledge effectively in their work settings. In response to the requirement for these professionals, PBL is a promising educational method. This paper suggests an educational development program for faculty to implement problem-based learning(PBL). To implement PBL at the higher educational level, there is a need for a systemic approach. First, a well-designed educational plan for PBL is necessary. Before implementing PBL, both the instructor and the students should be prepared. Faculty members should be well informed on the characteristics of PBL, effective tutoring or facilitation skills, and how to design problems reflecting features of their own academic subject areas. Students also have to know the characteristics of PBL. Both of these groups need to be trained through workshops rather than through lectures. Second, a phase of design and implementation of PBL is necessary. PBL methods may seem to be intuitive and even unstructured because a problem is, in nature, unstructured and authentic. However, a closer look at PBL reveals that it is complex, carefully designed, and highly structured activity. Therefore, if it is poorly and incompletely designed, PBL can be a frustrating and exhausting experience for students and faculty members. Well-designed PBL can be an exhilarating and rewarding experience for both of them. Third, a phase of sharing PBL experiences is important: faculty members who have implemented PBL are required to share their experiences to help others enhance tutoring skills, and acquire practical information of students, contents, and what happened during PBL, and to develop PBL model in a specific domain. Based on the developed PBL model in a specific domain, PBL can be expanded and stabilized at the university level.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1540-1551
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• 2015

The detection of position and speed in BLDC motors without using position sensors has meant many efforts for the last decades. The aim of this paper is to develop a sensorless technique for detecting the position and speed of BLDC motors, and to overcome the drawbacks of position sensor-based methods by improving the performance of traditional approaches oriented to motor phase voltage sensing. The position and speed information is obtained by computing the derivative of the terminal phase voltages regarding to a virtual neutral point. For starting-up the motor and implementing the algorithms of the detection technique, a FPGA board with a real-time processor is used. Also, a versatile hardware has been developed for driving BLDC motors through pulse width modulation (PWM) signals. Delta and wye winding motors have been considered for evaluating the performance of the designed hardware and software, and tests with and without load are performed. Experimental results for validating the detection technique were attained in the range 5-1500 rpm and 5-150 rpm under no-load and full-load conditions, respectively. Specifically, speed and position square errors lower than 3 rpm and between 10º-30º were obtained without load. In addition, the speed and position errors after full-load tests were around 1 rpm and between 10º-15º, respectively. These results provide the evidence that the developed technique allows to detect the position and speed of BLDC motors with low accuracy errors at starting-up and over a wide speed range, and reduce the influence of noise in position sensing, which suggest that it can be satisfactorily used as a reliable alternative to position sensors in precision applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2589-2594
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• 2012

In this paper, a novel resonator using ring type DGS is proposed for improvement of phase noise characteristics that is weak point of oscillator using planar type microstrip line resonator, and oscillator for 5.8 GHz band is designed using proposed DGS resonator. The ring type DGS resonator is composed of DGS cell etched on ground plane under $50{\Omega}$ microstrip line. At the fundamental frequency of 5.8 GHz, 7.6 dBm output power and -82.7 dBc@100kHz phase noise have been measured for oscillator with ring type DGS resonator. We designed the voltage controlled oscillator using proposed the DGS resonator with varactor diodes placed between gaps of DGS. Thus, due to its simple fabrication process and planar type, it is expected that the technique in this paper can be widely used for low phase noise oscillators for both MIC and MMIC applications.