• Journal of the Korea Safety Management & Science
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• v.3 no.1
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• pp.25-34
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• 2001

With the help of the Internet, communication with customers and the frequency and speed of the problem solving has improved greatly At this point mayor enterprises are paying much attention to CRM and their related markets are expanding rapidly I'll give a bnef introduction to the CRM system and go Into the problems that should be considered and which phase to emphasize when building this system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.425-429
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• 2002

In this paper, a single-phase inverter using a diode bridge-type resonant circuit to implement ZVT(Zero Voltage Transition) switching is presented. The current control algorithm is analyzed about how to design the circuit with auxiliary switch which can ZVT operation for the main power switch. The simulation and experimental results would be shown to verify the proposed current algorithm, because the main power switch is turn on with ZVT and the hi-directional inverter is operated.

• Journal of Applied Reliability
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• v.5 no.4
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• pp.451-463
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• 2005

This paper describes procedure to build a generic reliability analysis database structure and failure data during the conceptual design phase. Reliability prediction utilizing such supporting database system enable the designer to quantify the effects of varying design and operational constrains on mechanical component's failure rate. This leads to compare competing alternatives to the reliability improvement efforts.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.488-488
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• 2004

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.109-110
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• 2012

본 논문에서는 계통연계형 단상 충전기 전류제어기법 및 충전과 방전을 수행하는 제어기법을 서술하였다. 정전류-정전압 모드를 통해 충전을 하며, 유효-무효전력 제어를 통해 방전을 수행하게 되고, 동기좌표 PI 제어기를 적용하여 전류제어를 수행한다. 5kW급 계통연계형 단상 충전기 프로토타입을 제작하여, 제안한 동작모드를 실험하여 그 성능을 확인하였다.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.316-317
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• 2020

In this paper, a novel six-level inverter is proposed. Voltage regulation is applied at DC-link and flying capacitors through the implementation of phase-shifted carrier-based modulation with zero-sequence voltage injection. The performance of the proposed structure has been verified under various modulation indices, where low voltage ripple is achieved at each capacitor and total harmonic distortions (THD) of line voltage at unity modulation index is about 15.95%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1028-1033
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• 2014

We investigate the OFDM-based wireless LAN systems operating in the 60 GHz frequency band as part of the fourth-generation (4G) systems. The 60 GHz band is of much interest since this is the band in which a massive amount of spectral space has been allocated worldwide for dense wireless local communications. This paper gives an overview of 60 GHz band channel characteristics and an effect on phase noise. The performance of OFDM system is severely degraded by the local oscillator phase noise, which causes both common phase error and inter-carrier interference. In this paper, we apply phase noise suppression (PNS) algorithm that is easy for implementation to OFDM based 60 GHz wireless LAN system and analyze the SER performance. In case of using the PNS algorithm, SER performance is improved about 6 dB, 7.5 dB, respectively in 16, 64-QAM.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.171-177
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• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.

• Information Systems Review
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• v.8 no.1
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• pp.241-263
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• 2006

Since 1995 many enterprises have introduced ERP to strengthen competitive power. However, enterprises that have introduced ERP for the first time have experienced various types of problems integrating them; to this day, there are only a few enterprises that have implemented ERP successfully. The main reason for the failures of successful ERP implementing is that enterprises frequently ignore and/or don't know how to systematically evaluate the construction process of ERP and busy finishing a phase without resolving problems before going on to the next phase. This research focused on the implementation process of ERP project to evaluate the process of ERP at each phase. As a result, we propose an evaluation model of ERP project as a tool to find critical problems at each phase and improve on how to resolve the problems found at each phase. This evaluation model makes it possible to introduce ERP successfully by presenting the basis of assessment which will be used by enterprises to minimize the trial and error of construction process of ERP.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1156-1164
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• 1999

In this paper, we have studied the 8 YSB (8 Vestigial Side Band) method which is decided as the standard of modulators for next generation digital TV System. In developing digital TV System, one of the difficult problems is how digital signal can be transmitted to the receiver without any phase distortion. But, phase error is liable to occur by imperfect design, circumstance variation and device degradation. These characteristics result in distortion of 1,0 signal of modulator and interference in adjacent channels. In particular, the interference in modulator of a high power amplifier result in serious problems in adjacent channels. Here we analyzed problems of phase error which are occurred when 8 levels digital signals are modulated to If signal. And we suggested phase error compensation algorithm and discussed the results for adaptation of the algorithm