• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.205-208
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• 2002

The stand-alone transmission system design on compressed still image using DSP processor and Wavelet is presented. The target system is based on 32bits DSP processor. The image is compressed with Wavelet. The system for NTSC format image signal is able to transmit still image data to be high speed and is applicable to a surveillance and inspection system independently.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.2 s.25
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• pp.111-117
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• 2006

This paper describes the design principles and methods of electronic processor for thermal imager with 320$\times$240 staring array infrared detector. For the detector's nonuniformity correction and excellent image quality, we have designed the multi-point correction method using the defocusing technique of the optics. And to enhance the image of low contrast and improve the detection capability, the new technique of histogram processing has been designed. Through these image processing techniques, we have developed the high quality thermal imager and acquired a satisfactory thermal image. The result of MRTD(Minimum Resolvable Temperature Difference) is $0.1^{\circ}C$ at 4cycles/mard.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.561-564
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• 2009

This paper present design and implementation of U-city infrared image surveillance system based on the digital media processor. The hardware is designed and implemented by using commercial chips such as DM642 processor and video encoder, video decoder and the functions of software are to analyze temperature distribution of a monitoring image and to monitor disaster situation such as fire. The required functions and performances are confirmed by testing of the prototype and we verified practicality of the system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.8
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• pp.1085-1090
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• 1995

The Discrete Cosine Transform(DCT) is effective technique for image compression, which is widely used in the area of digital signal processing. In this paper, an efficient DCT processor is proposed and simulated by using Verilog HDL. This algorithm is improved 60% in processing speed, but it's somewhat complicate compared with Y. Arai's algorithm. This algorithm will be used efficiently for real time image processing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.555-562
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• 2007

In order to display Bayer input stream received from CMOS image sensor to the display device, image signal processing must be performed. That is, the hardware performing the image signal processing for Bayer data is called ISP(Image Signal Processor). We can see real image through ISP processing. ISP executes functionalities for gamma correction, interpolation, color space conversion, image effect, image scale, AWB, AE and AF. In this paper, we obtained the optimum algorithm through software verification of ISP module for CMOS camera image sensor and described using VHDL and verified in ModelSim6.0a simulator. Also we downloaded into Xilinx XCV-1000e for the designed ISP module and completed the board level verification using PCI interface.

• The KIPS Transactions:PartA
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• v.18A no.2
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• pp.45-52
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• 2011

In the past, a patient went to the room where an ultrasound image diagnosis device was set, and then he or she was examined by a doctor. However, currently a doctor can go and examine the patient with a handheld ultrasound device who stays in a room. However, it was implemented with only fundamental functions, and can not meet the high performance required by the focusing algorithm of ultrasound beam which determines the quality of ultrasound image. In addition, low energy consumption was satisfied for the mobile ultrasound device. To satisfy these requirements, this paper proposes a high-performance and low-power single instruction, multiple data (SIMD) based multi-core processor that supports a representative beamforming algorithm out of several focusing methods of mobile ultrasound image signals. The proposed SIMD multi-core processor, which consists of 16 processing elements (PEs), satisfies the high-performance required by the beamforming algorithm by exploiting considerable data-level parallelism inherent in the echo image data of ultrasound. Experimental results showed that the proposed multi-core processor outperforms a commercial high-performance processor, TI DSP C6416, in terms of execution time (15.8 times better), energy efficiency (6.9 times better), and area efficiency (10 times better).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.56-70
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• 2010

Rendering technique generating 2 dimensional image to give reality and high performance graphical processor for efficient processing of massive data are necessary to support realistic 3 dimensional graphical image. Recently, graphical hardwares have evolved rapidly. This enables high quality rendering effect that we were unable to process in realtime. Improving shading technique enabled us to render realistic images but still much time is required for this process. Multiple operational units are being integrated in a graphical processor for effective floating point operation using massive data to process almost real looking images. In this paper, we have designed and implemented a special functional unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed special functional unit. Hardware resource usage rate and execution speed are measured implementing directly on FPGA Virtex-4(xc4vlx200).

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.303-317
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• 2002

In this paper, we design and implement E-COIRS enabling users to query with concepts and image features used for further refining the concepts. For example, E-COIRS supports the query "retrieve images containing black home appliance to north of reception set. "The query includes two types of concepts: IS-A and composite. "home appliance"is an IS-A concept, and "reception set" is a composite concept. For evaluating such a query. E-COIRS includes three important components: a visual image indexer, thesauri and a query processor. Each pair of objects in an mage captured by the visual image indexer is converted into a triple. The triple consists of the two object identifiers (oids) and their spatial relationship. All the features of an object is referenced by its old. A composite concept is detected by the triple thesaurus and IS-A concept is recolonized by the fuzzy term thesaurus. The query processor obtains an image set by matching each triple in a user with an inverted file and CS-Tree. To support efficient storage use and fast retrieval on high-dimensional feature vectors, E-COIRS uses Cell-based Signature tree(CS-Tree). E-COIRS is a more advanced content-based image retrieval system than other systems which support only concepts or image features.

• Journal of the Korea Society of Computer and Information
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• v.16 no.8
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• pp.119-128
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• 2011

This paper introduces design space exploration of many-core processors that meet high performance and low power required by the beamforming algorithm of image signals of mobile ultrasound. For the design space exploration of the many-core processor, we mapped different number of ultrasound image data to each processing element of many-core, and then determined an optimal many-core processor architecture in terms of execution time, energy efficiency and area efficiency. Experimental results indicate that PE=4096 and 1024 provide the highest energy efficiency and area efficiency, respectively. In addition, PE=4096 achieves 46x and 10x better than TI DSP C6416, which is widely used for ultrasound image devices, in terms of energy efficiency and area efficiency, respectively.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.1
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• pp.25-29
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• 2013

Recently ARM processor's processing power has been increasing rapidly as it has been applied to consumer electronics products. Because of its computing power and low power consumption, it is used to various embedded systems.( including vision processing systems.) Embedded linux that provides well-made platform and GUI is also a powerful tool for ARM based embedded systems. So short period to develop is one of major advantages to the ARM based embedded system. However, for real-time date processing applications such as an image processing system, ARM needs additional equipments such as FPGA that is suitable to parallel processing applications. In this paper, we developed an embedded system using ARM processor and FPGA. FPGA takes time consuming image preprocessing and numerical algorithms needs floating point arithmetic and user interface are implemented using the ARM processor. Overall processing speed of the system is 60 frames/sec of VGA images.