• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.283-290
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• 2006

The cellular neural networks have the structure that consists of an array of the same cell which is a simple processing element, and each of the cells has local connectivity and space invariant template properties. So, it has a very suitable structure for the hardware implementation. But, it is impossible to have a one-to-one mapping between the CNN hardware processors and the pixels of the practical large image. In this paper, a $5{\times}5$ CNN hardware processor with pipeline input and output that can be applied to the time-multiplexing processing scheme, which processes the large image with a small CNN cell block, is designed. the operation of the implemented $5{\times}5$ CNN hardware processor is verified from the edge detection and the shadow detection experimentations.

• The Transactions of the Korea Information Processing Society
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• v.4 no.10
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• pp.2553-2561
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• 1997

In this paper, a hardware architecture to calculate straight-line Hough transform algorithm for image recognition is suggested. This processor consists of the filtering module for gradient calculation and the HT calculation module, and the angle information are stored in memory table. For the suggested architecture, firstly, algorithm simulation is executed using C language to confirm the operation and to decide the precision of calculation, and secondly, architecture simulation is executed using VHDL language for the total blocks. According to C & VHDL simulation results, it is confirmed that the calculated data value is similarly obtained and the calculation defference is decreased as image clarity and bits increase.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.8-14
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• 2012

Improving the speed of image processing is in great demand according to spread of high quality visual media or massive image applications such as 3D TV or movies, AR(Augmented reality). SIMD computer attached to a host computer can accelerate various image processing and massive data operations. MAMS is a multi-access memory system which is, along with multiple processing elements(PEs), adequate for establishing a high performance pipelined SIMD machine. MAMS supports simultaneous access to pq data elements within a horizontal, a vertical, or a block subarray with a constant interval in an arbitrary position in an $M{\times}N$ array of data elements, where the number of memory modules(MMs), m, is a prime number greater than pq. MAMS-PP4 is the first realization of the MAMS architecture, which consists of four PEs in a single chip and five MMs. This paper presents implementation of image processing algorithms and performance analysis for MAMS-PP16 which consists of 16 PEs with 17 MMs in an extension or the prior work, MAMS-PP4. The newly designed MAMS-PP16 has a 64 bit instruction format and application specific instruction set. The author develops a simulator of the MAMS-PP16 system, which implemented algorithms can be executed on. Performance analysis has done with this simulator executing implemented algorithms of processing images. The result of performance analysis verifies consistent response of MAMS-PP16 through the pyramid operation in image processing algorithms comparing with a Pentium-based serial processor. Executing the pyramid operation in MAMS-PP16 results in consistent response of processing time while randomly response time in a serial processor.

• Journal of the Korea Computer Graphics Society
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• v.30 no.3
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• pp.81-86
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• 2024

The Image Signal Processor (ISP) converts RAW images captured by the camera sensor into user-preferred sRGB images. While RAW images contain more meaningful information for image processing than sRGB images, RAW images are rarely shared due to their large sizes. Moreover, the actual ISP process of a camera is not disclosed, making it difficult to model the inverse process. Consequently, research on learning the conversion between sRGB and RAW has been conducted. Recently, the ParamISP[1] model, which directly incorporates camera parameters (exposure time, sensitivity, aperture size, and focal length) to mimic the operations of a real camera ISP, has been proposed by advancing the simple network structures. However, existing studies, including ParamISP[1], have limitations in modeling the camera ISP as they do not consider the degradation caused by lens shading, optical aberration, and lens distortion, which limits the restoration performance. This study introduces Positional Encoding to enable the camera ISP neural network to better handle degradations caused by lens. The proposed positional encoding method is suitable for camera ISP neural networks that learn by dividing the image into patches. By reflecting the spatial context of the image, it allows for more precise image restoration compared to existing models.

• Journal of Information Processing Systems
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• v.1 no.1 s.1
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• pp.27-31
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• 2005

Vehicle detector system based on image processing technology is a significant domain of ITS (Intelligent Transportation System) applications due to its advantages such as low installation cost and it does not obstruct traffic during the installation of vehicle detection systems on the road[1]. In this paper, we propose architecture for vehicle detection by using image processing. The architecture consists of two main parts such as an image processing part, using high speed FPGA, decision and calculation part using CPU. The CPU part takes care of total system control and synthetic decision of vehicle detection. The FPGA part assumes charge of input and output image using video encoder and decoder, image classification and image memory control.

• Journal of the Korea Society for Simulation
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• v.10 no.3
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• pp.59-70
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• 2001

Typical low-level image processing tasks require thousands of operations per pixel for each input image. Traditional general-purpose computers are not capable of performing such tasks in real time. Yet important features of traditional computers are not exploited by low-level image processing tasks. Since storage requirements are limited to a small number of low-precision integer values per pixel, large hierarchical memory systems are not necessary. The mismatch between the demands of low-level image processing tasks and the characteristics of conventional computers motivates investigation of alternative architectures. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. In this paper we implemented various image processing filtering using the format converter. Also, we realized from conventional gray image process to color image process. This design method is based on realized the large processor-per-pixel array by integrated circuit technology This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.3
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• pp.49-57
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• 2002

In this paper, we deal with a real time implementation of the integrated image-based navigation parameter extraction system using the TMS320C80 MVP(multimedia video processor). Our system consists of relative position estimation and absolute position compensation, which is further divided into high-resolution aerial image matching, DEM(Digital elevation model) matching, and IRS (Indian remote sensing) satellite image matching. Those algorithms are implemented in real time using the MVP. To achieve a real-time operation, an attempt is made to partition the aerial image and process the partitioned images in parallel using the four parallel processors in the MVP. We also examine the performance of the implemented integrated system in terms of the estimation accuracy, confirming a proper operation of the our system.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.4
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• pp.169-175
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• 2005

In recent, implementation of the embedded system is gradually in the spotlight of world-wide by information technology(IT) engineers. By this time, an implementation of real time system is limited on image acquisition and processing system in practical. In this paper, the USB camera interface system based on the embedded linux OS is implemented using USB 2.0 camera with low cost. This system can obtain image signals into the memory via X-hyper255B processor from USB camera. It is need to initialize USB camera by the Video4Linux for the kernel device driver. From the system image capturing and image processing can be performed. It is confirmed that the image data can be transformed to packet of Network File System(NFS) and connected to the internetwork, then the data can be monitored from the client computer connected to the internetwork.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.477-481
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• 2004

High Quality CD, OAT audio requires that large amount of data. Currently, multi channel preference has been rapidly propagated among latest users. The MPEG(Moving Picture Expert Group) is provides data compression technology of sound and image system. The MPEG standard provides multi channel and 5.1 sounds, using the same audio algorithm as MPEG-l. And MPEG-2 audio is forward and backward compatible. The MDCT (Modified Discrete Cosine Transform) is a linear orthogonal lapped transform based on the idea of TDAC(Time Domain Aliasing Cancellation). In this paper, we proposed the micro-program type vector processor architecture a benefit in MDCT/IMDCT of MPEG-II AAC. And it's reduced operating coefficient by overlapped area to bind. To compare original algorithm with optimized algorithm that cosine coefficient reduced $0.5\%$multiply operating $0.098\%$ and add operating 80.58\%$. Algorithm test is used C-language then we designed hardware architecture of micro-programmed method that applied to optimized algorithm. This processor is 20MHz operation 5V.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.489-492
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• 2000

본 논문에서는 영상 항법 변수 추출 알고리듬의 실시간 구현에 관해 연구하였다. 영상 항법 변수 추출 알고리듬은 이전 위치를 기준으로 현재 위치를 추정해내는 상대위치 추정 알고리듬과 상대위치 추정에 의해 누적되는 오차를 보정하기 위한 절대위치 보정 알고리듬으로 구성된다. 절대위치 보정 알고리듬은 고해상도 영상과 IRS (Indian Remote Sensing) 위성영상을 기준영상으로 이용하는 방법 및 DEM (Digital Elevation Model) 을 이용하는 방법으로 구성된다. 하이브리드 영상 항법 변수 추출 알고리듬을 실시간으로 구현하기 위해 MVP (Multimedia Video Processor)로 명명된 TMS320C80 DSP (Digital Signal Processor) 칩을 사용하였다. 구현된 시스템은 MVP의 부동 소수점 프로세서인 MP (Master Processor) 를 고정 소수점 프로세서인 PP (Parallel Processor) 를 제어하거나 삼각함수 계산과 같은 부동 소수점 함수를 계산하는데 사용하였고, 대부분의 연산은 PP를 사용하여 수행하였다. 처리시간이 많이 필요한 모듈에 대해서는 고속 알고리듬을 개발하였고, 4개의 PP를 효율적으로 사용하기 위한 영상분할 방법에 대해 제안하였다. 비행체에서 캡코더를 이용해 촬영한 연속 항공 영상과 비행체의 자세정보를 입력으로 실시간 시뮬레이션 하였다. 실험결과는 하이브리드 항법 변수 추출 알고리듬의 실시간 구현이 효과적으로 구현되었음을 나타내고 있다.