• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.1
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• pp.30-38
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• 1995

In this paper, we propose an efficient architecture for motion estimation processor which performs one of essential functions in moving picture coding algorithms. Simple control mechanism of data flow in register array which stores pixel data, parallel processing of pixel data and pipelining scheme in arithmetic umit allow this architecture to process a 352*288 pixel image at the frame rate of 30fs, which is compatable with CCITT standard H.261.

• Journal of Internet Computing and Services
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• v.21 no.5
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• pp.149-157
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• 2020

Recently, as interest in artificial intelligence has increased, many studies have been conducted to implement AI processors. However, the AI processor requires functional verification as well as performance verification on whether the AI processor is suitable for the application. In this paper, We propose an AI processor performance analyzer that can verify the application performance and explore the limitations of the processor. By Using the performance analyzer, we explore the limitations of the AI processor and optimize the AI model to fit an AI processor in image recognition and speech recognition applications.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.473-480
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• 2009

This paper is to enhance a color image running in the PXA255 ARM processor based on embedded linux environments. Retinex is one of the representative algorithm for image enhancement in the previous research. However, retinex is not suitable the run on the embedded system because of its long processing time. So, we proposed the image enhancement algorithm for embedded system, with less quantity of operation and the effect equivalent to retinex. To achieve this goal, we propose and implement the image enhancement algorithm, which utilizes the image formation model and gamma correction to be effective in a back-light and dark image. The proposed algorithm converts the color space from RGB to HSV, and then V and S channels are processed. In order to optimize the proposed method in the PXA255 ARM processor, quantity of calculation is reduced. The performance of the proposed algorithm was evaluated through qualitative method and quantitative method. The results show that brightness and contrast are improved with less quantity of operation.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1565-1567
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• 2004

Various defects are found in FPD (Flat Panel Display) manufacturing process. So detecting these defects early and reprocessing them is an important factor that reduces the cost of production. In this paper, the bare glass inspection system for the FPD which is the early process inspection system in the FPD manufacturing process is designed and implemented using the high performance and accuracy CCD line scan camera. For the preprocessing of the high speed line image data, the Image Processing Part (IPP) is designed and implemented using high performance DSP (Digital signal Processor), FIFO (First in First out), FPGA (Field Programmable Gate Array) and the Data Management and System Control part are implemented using ARM (Advanced RISC Machine) processor to control many IPP and cameras and to provide remote users with processed data. For evaluating implemented system, experiment environment which has an area camera for reviewing and moving shelf is made.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2677-2680
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• 2003

This paper describes the implementation of a 4 channel embedded DVR system. It receives analog video from CCD cameras and converts to 640${\times}$480 CCIR-656 digital video by 30 frames/sec. These digital images are compressed to the wevelet transformed image using hardware codec which is capable of 350:1 real-time compression and decompression. The DVR is working on linux and it implemented on an embedded system which is based on StrongARM processor. For the interface between processor system module and image processing module, GPIO and memory control module are used, device drivers are developed. Linux kernel source is customized. This paper provides techniques of embedded system development and embedded linux porting.

• Transactions of the Korean Society of Mechanical Engineers
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• v.19 no.6
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• pp.1382-1390
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• 1995

Electronic Speckle Pattern Interferometry (ESPI) with a CW laser, a video system and an image processor was utilized to measure the in-plane displacement. Unlike traditional strain gauges or Moire method. ESPI method measure the in-plane displacement on real time with out any surface preparation on surface attachment. The specimen has a crack of 10*0.1 mm in the middle of plate and strain gauge was also attached on that surface to compare with ESPI method. This study reveled the ESPI method to measure the displacement and distribution of strain in the specimen. It was shown in tensile tests that the measurement by ESPI method was comparable with strain gauge.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.425-427
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• 2004

Many of the problems by using the microscope are related to the fact that the eyes of the surgeon must be continually fixed to the microscope eyepieces. In this paper, we describe a development of the stereoscopic monitoring system of the stereo microscope for reduced eyestrain or operator fatigue about the long time observations of the microscope. The system consists of the stereoscopic camera part, the stereoscopic image processor device and the polarized light stereoscopic monitor. The left and right images obtained form the two CCD cameras are the same as the eyepiece images. By use of the image processor, the polarized light stereoscopic monitor displayed a real-time stereo microscope images.

• Journal of the Korean Institute of Navigation
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• v.24 no.5
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• pp.435-441
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• 2000

This paper deals with the development of RACOM(Radar Signal Detecting ＆ Processing Computer). RACOM is a radar display system specially designed for radar scan conversion, signal processing and PCI radar image display. RACOM contains two components； i )RSP(Radar Signal Processor) board which is a PCI based board for receiving video, trigger, heading & bearing signals from radar scanner ＆ tranceiver units and processing these signals to generate high resolution radar image, and ⅱ）Applications which perform ordinary radar display functions such as EBL, VRM and so on. Since RACOM is designed to meet a wide variety of specifications(type of output signal from tranceiver unit), to record radar images and to distribute those images in real time to everywhere in a networked environment, it can be applicable to AIS(Automatic Identification System) and VDR(Voyage Data Recorder).

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.835-838
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• 1998

본 연구에서는 칼라 CCD 센서를 제어하여, shading과 .gamma. correction 된 데이터를 읽어 들여, 이를 이진레벨 데이터로 바꾼후, 원래의 다치레벨 또는 이진레벨 데이터를 SCSI나 DMA I/F를 통해 전달하는 ASIC을 설계하였다. 본 ASIC에서는 이진화를 위하여 문자 모드에서는 simple threshold와 LAT(local adaptive threshold) 알고리즘을, 그림모드에서는 stucki error diffusion 알고리즘을 적용하였다. 그리고, 구성은 CCD센서 제어블락, 스텝 모타 제어제어블락, 이미지 축소블락, 데이터 이진화 블락, 그리고 DATA I/F 블락 등으로 이루어져 있다. 또한 사용된 technology는 삼성 0.5um CMOS standard cell이며, 크기는 45K gates(내부 메모리 제외)이고, 160QFP package로 구현되었다. ㅎㅁㅅㄷㄴ (soqn apa

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.110-119
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• 1996

A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.