An efficient architecture for motion estimation processor satisfying CCITT H.261

CCITT H.261를 위한 효율적인 구조의 움직임 추정 프로세서 VLSI 설계

In this paper, we propose an efficient architecture for motion estimation processor which performs one of essential functions in moving picture coding algorithms. Simple control mechanism of data flow in register array which stores pixel data, parallel processing of pixel data and pipelining scheme in arithmetic umit allow this architecture to process a 352*288 pixel image at the frame rate of 30fs, which is compatable with CCITT standard H.261.