• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.197-199
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• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

• Bulletin of the Korean Space Science Society
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• 2011.04a
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• pp.32.2-32.2
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• 2011

State dependent Riccati equation (SDRE) control technique has been widely used in the control society. Although it solves nonlinear optimal control problems, which minimizes state error and control efforts simultaneously, it has drawbacks when it is to be applied to the real time systems in that it requires much computational efforts. So the real time system whose computational ability is limited (for example, satellites) cannot afford to use SDRE controller. To solve this problem, a hybrid controller which is based on MSDRE (Modified SDRE) and ANFIS (Adaptive Neuro-Fuzzy Inference System) has been proposed by Abdelrahman et al. (2010). We propose a hybrid controller based on SDRE and ANFIS, and apply the hybrid controller to the hardware attitude simulator to perform a HIL (Hardware-In-the-Loop) simulation. Through HIL simulation, it is demonstrated that the hybrid controller satisfies the control requirement and the computation load is reduced significantly. In addition, the effects of statistical properties of the ANFIS training data to the performance of the ANFIS controller have been analyzed.

• Journal of Korea Multimedia Society
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• v.4 no.1
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• pp.82-90
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• 2001

Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. This paper proposes a new type of embedded one chip computer fort Hardware Implementation of Genetic Algorithm. The proposed embedded one chip computer consists of 16 Bit CPU care and hardware of genetic algorithm. In contrast to conventional hardware oriented GA which is dependent on main computer in the process of GA, the proposed embedded one chip computer is independent on main computer. Conventional hardware GA uses the fixed length of chromosome but the proposed embedded one chip computer uses the variable length of chromosome by employing the efficient 16 bit Pipeline Unit. Experimental results show that the proposed one chip computer is applicable to the design of evolvable hardware for Random NRZ bit synchronization circuit.

• Journal of Information Processing Systems
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• v.15 no.6
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• pp.1406-1421
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• 2019

The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.466-468
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fired length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1553-1557
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• 2004

A real-time processing system for embedded hardware genetic algorithm is suggested. In order to operate basic module of genetic algorithm in parallel, such as selection, crossover, mutation and evaluation, dual processors based architecture is implemented. The system consists of two Xscale processors and two FPGA with evolvable hardware, which enables to process genetic algorithm efficiently by distributing the computational load of hardware genetic algorithm to each processors equally. The hardware genetic algorithm runs on Linux OS and the resulted chromosome is executed on evolvable hardware in FPGA. Furthermore, the suggested architecture can be extended easily for a couple of connected processors in serial, making it accelerate to compute a real-time hardware genetic algorithm. To investigate the effect of proposed approach, performance comparisons is experimented for an typical computation of genetic algorithm.

• ETRI Journal
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• v.33 no.4
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• pp.611-620
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• 2011

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.718-723
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA. Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fixed length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.10
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• pp.983-990
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• 2008

This paper presents the fault detection and diagnosis(FDD) algorithm to enhance reliability of a longitudinal controller for an autonomous All-Terrain Vehicle(ATV). The FDD is designed to monitor and identify faults which may occur in distributed hardware used for longitudinal control, e.g., DSPs, CAN, sensors, and actuators. The proposed FDD is an integrated approach of decentralized and centralized FDD. While the former is processed in a DSP and suitable to detect faults in a single hardware, it is sensitive to noise and disturbance. On the other hand, the latter is performed via communication and it detects and diagnoses faults through analyzing concurrent performances of multiple hardware modules, but it is limited to isolate faults specifically in terms of components in the single hardware. To compensate for disadvantages of each FDD approach, two layered structure including both decentralized and centralized FDD is proposed and it allows us to make more robust fault detection and more specific fault isolation. The effectiveness of the proposed method will be validated experimentally.

• Transactions of the Korean Society of Automotive Engineers
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• v.15 no.6
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• pp.23-29
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• 2007

In Korea, the number of LPG vehicles is increasing continuously because LPG is cheaper than Gasoline. Also in Europe, the CNG fuel is a good solution to meet $CO_2$ regulation. In order to use LPG/CNG fuel, new EMS ECU must be developed for every type of vehicles and it requires huge development cost. In order to reduce development cost and time, SIEMENS VDO has developed an Interface Box. It supports EMS ECU in the car and manages LPG/CNG fuel injection system. Basically the Interface box can be used with any kind of EMS ECU. The Interface Box controls LPG/CNG injector through the injection command of gasoline EMS ECU. It calculates required amount of based on the fuel temperature and pressure and sends feedback signal to ECU for fuel correction. Also, it controls LPG/CNG specific actuator such a Shut off valves and LPG switch inputs.