• Title/Summary/Keyword: IT Hardware

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FPGA Design of High-performance Display Converter (고성능 디스플레이 변환기의 FPGA 설계)

  • Choi, Hyun-Jun;Seo, Young-Ho;Kim, Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.8
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    • pp.1895-1900
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    • 2010
  • In this paper, we propose the hardware architecture of a display converter which is consisted of four functional blocks. The four functional blocks consists of a set of color space converter, de-interacer, video display scaler, and gamma corrector. After the proposed architecture was implemented into hardware, we verified that it operated exactly. The designed hardware has 7,629 LUT and 6,800 Logic Register in Stratix device of Altera and operates in 270 MHz clock frequency.

A Study on Optimization of Hardware Complexity of a FFT Processor for IEEE 802.11n WLAN (IEEE 802.11n WLAN을 위한 FFT 프로세서의 하드웨어 복잡도 최적화에 대한 연구)

  • Choi, Rakhun;Park, Jungjun;Lim, Taemin;Lee, Jinyong;Kim, Younglok
    • IEMEK Journal of Embedded Systems and Applications
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    • v.6 no.4
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    • pp.243-248
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    • 2011
  • A FFT/IFFT processor is the key component for orthogonal frequency division multiplexing (OFDM) systems based IEEE 802.11n wireless local area network (WLAN). There exists many radix algorithms according to the structure of butterfly as FFT sub-module, each has the pros and cons on hardware complexity. Here, mixed radix algorithms for 64 and 128 FFT/IFFT processors are proposed, which reduce hardware complexity by using mixture of radix-23 and radix-4 algorithms. The proposed algorithm finish calculation within 3.2${\mu}s$ in order to meet IEEE 802.11n standard requirements and it has less hardware complexity compared with conventional algorithms.

A Hardware Implementation of SIMECK-64/128 Block Cipher Algorithm (SIMECK-64/128 블록암호 알고리듬의 하드웨어 구현)

  • Kim, Min-Ju;Jeong, Young-su;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2021.10a
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    • pp.229-231
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    • 2021
  • In this paper, we describe a hardware design of the SIMECK block cipher algorithm that can be implemented in lightweight hardware with appropriate security strength. To achieve fast encryption and decryption operations, it was designed using two-step method that reduces the number of operation rounds. The designed SIMECK cryptographic core was implemented in Arty S7-50 FPGA device and its hardware operation was verified with a GUI using Python.

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IoT based Pure Tone Audiometer with Software Platform Compatibility (IoT 기반의 소프트웨어 플랫폼 호환성을 갖는 순음청력 검사기)

  • Kang, Sung Ho;Lee, Jyung Hyun;Kim, Myoung Nam;Seong, Ki Woong;Cho, Jin-Ho
    • Journal of Korea Multimedia Society
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    • v.21 no.2
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    • pp.261-270
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    • 2018
  • Hearing-impaired people are increasing rapidly due to the global aging trend. Early detection of hearing loss requires an easy-to-use audiometry device for the public. Existing audiometry systems were developed as PC-based, PDA-based, or smartphone apps. These devices were often dependent on specific software platforms and hardware platforms. In this paper, we tried to improve software platform compatibility by using cross platform, and tried to implement IoT-based pure tone audiometry device which does not require sound pressure level correction due to hardware differences. Pure tone audiometry is available in a variety of ways depending on the type of hearing loss and age. Using the IoT-based audiometry device implemented in this paper, it will be possible for an app developer who lacks hardware knowledge to easily develop an app with various scenarios for hearing screening. The results of this study will contribute to overcoming the software and hardware dependency in the development of IoT-based healthcare device.

Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2m) for Irreducible Polynomials

  • Mathe, Sudha Ellison;Boppana, Lakshmi
    • ETRI Journal
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    • v.39 no.4
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    • pp.570-581
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    • 2017
  • Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.

Evaluation of Three-Phase Actuated Operation at Diamond Interchanges (다이아몬드 인터체인지의 3현시 감응제어 평가)

  • 이상수
    • Journal of Korean Society of Transportation
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    • v.20 no.2
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    • pp.149-159
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    • 2002
  • The performance of two single-barrier three-phase control systems at diamond interchanges was evaluated for various traffic conditions. To emulate the actuated signal control, hardware-in-the-loop system combined with CORSIM simulation program was used. Two performance measures, average delay and total stops, were used for the evaluation process. Results showed that the two three-phase systems gave similar performance in terms of average delay, but not stops. The delay performance of each phasing system was generally dependent on the traffic pattern and ramp spacing. However, there was a distinct movement preference for each phasing system. The total stops decreased as the spacing increased, and it was the most sensitive variable that can differentiate between the two three-phase systems. It was also shown that the hardware-in-the-loop control could be a good method to overcome the limitations of current simulation technology.

Design of 1-D DCT processor using a new efficient computation sharing multiplier (새로운 연산 공유 승산기를 이용한 1차원 DCT 프로세서의 설계)

  • Lee, Tae-Wook;Cho, Sang-Bock
    • The KIPS Transactions:PartA
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    • v.10A no.4
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    • pp.347-356
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    • 2003
  • The OCT algorithm needs efficient hardware architecture to compute inner product. The conventional methods have large hardware complexity. Because of this reason. a computation sharing multiplier was proposed for implementing inner product. However, the existing multiplier has inefficient hardware architecture in precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we proposed a new efficient computation sharing multiplier and applied it to implementation of 1-D DCT processor. The comparison results show that the new multiplier is more efficient than an old one when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using the proposed multiplier is more high performance than typical design methods.

Development of Brake Controller for fixed-wing aircraft using hardware In-the-Loop Simulation

  • Lee, Ki-Chang;Jeon, Jeong-Woo;Hwang, Don-Ha;Kim, Yong-Joo
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.535-538
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    • 2005
  • Today, most fixed-wing aircrafts are equipped with the antiskid brake system. It can modulate braking moments in the wheels optimally, when an aircraft is landing. So it can reduce landing distance and increase safeties. The antiskid brake system for an aircraft are mainly composed of braking moment modulators (hydraulic control valves) and brake control unit. In this paper, a Mark IV type - fully digital - brake controller is studied. For the development of its control algorithms, a 5-DOF (Degree of Freedom) aircraft landing model is composed in the form of matlab/simulink model at first. Then, braking moment control algorithms using wheel decelerations and slips are made. The developed algorithms are tested in software simulations using state-flow toolboxes in matlab/simulink model. Also, a real-time simulation systems are made, which use hydraulic brake systems of a real aircraft, pressure control valves and its controller as hardware components of HIL(Hardware In-the-Loop) simulation. Algorithms tested in software simulations are coded into the controller and the real-time landing simulations are made in very severe road conditions. The real-time simulation results are presented.

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High-Performance VLSI Architecture for Stereo Vision (스테레오 비전을 위한 고성능 VLSI 구조)

  • Seo, Youngho;Kim, Dong-Wook
    • Journal of Broadcast Engineering
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    • v.18 no.5
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    • pp.669-679
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    • 2013
  • This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

A Design of a Cellular Neural Network for the Real Image Processing (실영상처리를 위한 셀룰러 신경망 설계)

  • Kim Seung-Soo;Jeon Heung-Woo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.2
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    • pp.283-290
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    • 2006
  • The cellular neural networks have the structure that consists of an array of the same cell which is a simple processing element, and each of the cells has local connectivity and space invariant template properties. So, it has a very suitable structure for the hardware implementation. But, it is impossible to have a one-to-one mapping between the CNN hardware processors and the pixels of the practical large image. In this paper, a $5{\times}5$ CNN hardware processor with pipeline input and output that can be applied to the time-multiplexing processing scheme, which processes the large image with a small CNN cell block, is designed. the operation of the implemented $5{\times}5$ CNN hardware processor is verified from the edge detection and the shadow detection experimentations.