• 제목/요약/키워드: IS50

검색결과 40,662건 처리시간 0.066초

Performance Analysis on Day Trading Strategy with Bid-Ask Volume (호가잔량정보를 이용한 데이트레이딩전략의 수익성 분석)

  • Kim, Sun Woong
    • The Journal of the Korea Contents Association
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    • 제19권7호
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    • pp.36-46
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    • 2019
  • If stock market is efficient, any well-devised trading rule can't consistently outperform the average stock market returns. This study aims to verify whether the strategy based on bid-ask volume information can beat the stock market. I suggested a day trading strategy using order imbalance indicator and empirically analyzed its profitability with the KOSPI 200 index futures data from 2001 to 2018. Entry rules are as follows: If BSI is over 50%, enter buy order, otherwise enter sell order, assuming that stock price rises after BSI is over 50% and stock price falls after BSI is less than 50%. The empirical results showed that the suggested trading strategy generated very high trading profit, that is, its annual return runs to minimum 71% per annum even after the transaction costs. The profit was generated consistently during 18 years. This study also improved the suggested trading strategy applying the genetic algorithm, which may help the market practitioners who trade the KOSPI 200 index futures.

An Algorithm for Generator Maintenance Scheduling Considering Transmission System (송전계통을 고려한 계통운용자의 발전기 예방정비계획 알고리즘에 관한 연구)

  • Han Seok-Man;Shin Young-Gyun;Kim Balho
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • 제54권7호
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    • pp.352-357
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    • 2005
  • In competitive electricity markets, the System Operator (SO) coordinates the overall maintenance schedules when the collective maintenance schedule reported to 50 by Gencos not satisfy the specified operating criteria, such as system reliability or supply adequacy. This paper presented a method that divides generator maintenance scheduling of the 50 into a master-problem and a sub-problem. Master-problem is schedule coordination and sub-problem is DC-optimal power flow. If sub-problem is infeasible, we use the algorithm of modifying operating criteria of master-problem. And, the 50 should use the open information only, because the information such as cost function of a generator and bidding Price is highly crucial for the strategies of profit maximization.

Transcranial Doppler Detection of Vasospasm Following Subarachnoid Hemorrhage (지주막하 출혈에 따른 Vasospasm에 대한 Transcranial Doppler의 임상적 적용)

  • Lee, Jun Hong
    • Annals of Clinical Neurophysiology
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    • 제1권1호
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    • pp.55-59
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    • 1999
  • Vasoconstriction of intracerebral arteries is the leading cause of delayed cerebral infarction and mortality following aneurysmal subarachnoid hemorrhage. Transcranial Doppler studies show and increase in the flow velocities of basal cerebral arteries, which usually start around day 4 following a subarachnoid hemorrhage, and peaking by days 7 to 14. Angiographic studies confirm the presence of at least some degree of MCA vasospasm when the flow velocities are higher than 100 cm/sec. Mean velocities in the 120 to 200 cm/sec range correspond to 25 to 50% luminal narrowing. MCA and ACA vsospasm is detected with around 90% specificity. Sensitivity is 80% and 50% respectively. A 200cm/sec threshold and rapid flow velocity increase exceeding 50 cm/sec on consecutive days, has been associated with subsequent infarction. Transcranial Doppler is also used to monitor the effects of endovascular treatment of vasospasm. Flow velocities decrease following successful angioplasty or papaverine infusion. Overall, transcranial Doppler studies are considered to have acceptable accuracy for the evaluation of vasospasm in aneurysmal subarachnoid hemorrhage, with limitations that have to be taken into consideration in the clinical setting.

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A 50 to 150 MHz PLL with a New Phase Frequency Detector suitable for Microprocessor Application (마이크로프로세서 응용에 적합한 새로운 구조의 위상/주파수 검출기를 가지는50 to 150 MHz PLL)

  • 홍종욱;이성연;정우경;이용석
    • Proceedings of the IEEK Conference
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    • 대한전자공학회 1999년도 추계종합학술대회 논문집
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    • pp.955-958
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    • 1999
  • We designed a phase locked loop (PLL), which is applicable to microprocessor clock generation application. The designed PLL has a new simple phase frequency detector (PFD) which eliminate dead-zone and has a good high frequency characteristic. The lock-in range of the designed PLL is 50 MHz ~ 150 MHz at 3.3v power supply voltage. The design is carried out using a 0.6${\mu}{\textrm}{m}$ triple metal CMOS process. The area of the layout is 0.35mm by 0.42mm with 359 transistors.

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An experimental study on the improvement of resistance performance by appendage for 50 knots class planing hull form (50노트급 활주형선의 저항성능 개선을 위한 부가물 부착에 관한 실험적 연구)

  • Lee, Kwi-Joo;Park, Na-Ra;Lee, Eun-Jung
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • 제41권3호
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    • pp.222-226
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    • 2005
  • A series of model tests carried out at the CWC of WJFEL for the purpose of prediction of resistance for the performance and improvement of resistance by attaching appendage for the ship of 50 knots class planing hull. The resistance performance evaluation has been carried out for the bare hull and for the appendage hull with two different depth of vertical type wedges. In the bare model test, trim and sinkage is calculated for the planing hull and the resistance is calculated. For minimizing the resistance, wedge appendage is attached and tested. Analysis and tests shows that for a 12.5mm wedge, resistance is minimum and overall power tallied to 5636ps.

A 3V-50MHz analog CMOS continuous time current-mode filter with a negative resistance load

  • 현재섭;윤광섭
    • The Journal of Korean Institute of Communications and Information Sciences
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    • 제21권7호
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    • pp.1726-1733
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    • 1996
  • A 3V-50MHz analog CMOS continuous-time current-mode filter with a negative resistance load(NRL) is proposed. In order to design a current-mode current integrator, a modified basic current mirror with a NRL to increase the output resistance is employed. the inherent circuit structure of the designed NRL current integrator, which minimizes the internal circuit nodes and enhances the gain bandwidth product, is capable of making the filter operate at the high frequency. The third order Butterworth low pass filter utilizing the designed NRL current integrator is synthesized and simulated with a 1.5.mu.m CMOS n-well proess. Simulation result shows the cutoff frequency of 50MHz and power consumption of 2.4mW/pole with a 3V power supply.

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A Study on Friction Coefficient Prediction of Hydraulic Driving Members by Neural Network (신경회로망에 의한 유압구동 부재의 마찰계수 추정 에 관한 연구)

  • 김동호
    • Transactions of the Korean Society of Machine Tool Engineers
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    • 제12권5호
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    • pp.53-58
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    • 2003
  • Wear debris can be collected from the lubricants of operating machinery and its morphology is directly related to the fiction condition of the interacting materials from which the wear particles originated in lubricated machinery. But in order to predict and estimate working conditions, it is need to analyze the shape characteristics of wear debris and to identify. Therefore, if the shape characteristics of wear debris is identified by computer image analysis and the neural network, The four parameter (50% volumetric diameter, aspect, roundness and reflectivity) of wear debris are used as inputs to the network and learned the friction. It is shown that identification results depend on the ranges of these shape parameters learned. The three kinds of the wear debris had a different pattern characteristic and recognized the friction condition and materials very well by neural network. We resented how the neural network recognize wear debris on driving condition.

Study on the high precision output of 50kV high-voltage inverter (50kV 고전압 인버터 고정밀 출력설계에 관한 연구)

  • Son, Y.G.;Suh, J.H.;Oh, J.S.;Cho, M.H.
    • Proceedings of the KIEE Conference
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    • 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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    • pp.2199-2201
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    • 2005
  • High voltage power supply with pulse load($4.5{\mu}s$ and PRF 60Hz) condition is investigated which is of interest for applications like Klystron modulator power supplies with output voltage of 50kV. The performance specifications with this type of power supplies are very stringent demanding tight regulation(<0.01%) and high efficiency(> 85%). The solution to this problem as a single stage converter is very difficult. The final output voltage is obtained as sum of the output of SCPS & PCPS. The combination of the two stages can satisfy the pulse load specifications. The analysis of the voltage and power division between SCPS & PCPS has been done for the proposed topology. It has studied under various operating conditions of line and load. Simulation results are validated by experimental results.

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Frozen Bread Dough: a Smart Technology

  • Le-Bail, Alain;Havet, Michel;Prost, Carole;Poinot, Pauline;Rannou, Cecile;Arvisenet, Gaelle;Jury, Vanessa;Monteau, Jean Yves;Chevallier, Sylvie;Loisel, Catherine
    • Food Science and Industry
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    • 제45권4호
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    • pp.21-28
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    • 2012
  • Bread making is based on several simple unit operations, basically kneading, fermentation and baking; however, it is still a quite complex process and bread quality can be strongly affected by minor details. The market of bread production is roughly shared at 50-50 between the industry market and the artisanal market, even though the frontier between these two players is not very easy. Different strategies have been developped by the industry to extend the shelf life of bread or to interrupt the bread making process. Freezing for example has been used form the 50s to extend the shelf life of bakery products. It was first applied to fully baked products and then to frozen dough which appeared as an interesting strategy to interrupt the bread making protocol. This paper presents a review on key issues of the frozen dough technology.

The propulsive plan on the standardization in 22.9kV, 50MVA HTS power cable (22.9kV, 50MVA급 초전도 전력케이블의 표준화 추진 방안)

  • Choi, S.J.;Lee, S.J.;Sim, K.D.;Cho, J.W.;Lee, S.K.
    • Progress in Superconductivity and Cryogenics
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    • 제10권1호
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    • pp.48-51
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    • 2008
  • The standardization on superconducting application techniques has been focused only in testing method or material itself, but, recently, it is actively proceeded by superconducting technical committee(TC) of international electro technical commission(IEC). In this paper, the standardization organization and its necessary process is introduced and the standardization technique for 22.9kV, 50MVA HTS power cable is prescribed. Throughout this research, it is possible to take priorities on the standardization technique in HTS power cable application. And moreover it can also contributes to the commercialization of HTS power cable.