• Journal of applied mathematics & informatics
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• v.17 no.1_2_3
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• pp.93-107
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• 2005

Based on the recently developed ABS algorithm for solving linear Diophantine equations, we present a special ABS algorithm for solving such equations which is effective in computation and storage, not requiring the computation of the greatest common divisor. A class of equations always solvable in integers is identified. Using this result, we discuss the ILP problem with upper and lower bounds on the variables.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.116-119
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• 2015

In this paper we propose an algorithm for environment monitoring using multiple mobile sensor (MS) nodes. Our focus is on maximizing sensing coverage of a group of MS nodes for monitoring a phenomenon in an unknown and open area over time. In the proposed algorithm, MS nodes are iteratively relocated to new positions at which a higher sensing coverage can be obtained. We formulated an integer linear programming (ILP) optimization problem to find the optimal positions for MS nodes with the objective of coverage maximization. The performance evaluation was performed to confirm that the proposed algorithm can enable MS nodes to relocate to high interest positions, and obtain a maximum sensing coverage.

• The Transactions of the Korea Information Processing Society
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• v.6 no.2
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• pp.497-511
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• 1999

Recently, many parallel processing technologies were developed, ILP(Instruction level Parallelism) processor's performance have been growed very rapidly. especially, EPIC(Explicitly Parallel Instruction computing) architectures attempt to enhance the performance in the predicated execution and speculative execution with the hardware. In this paper to improve the code scheduling possibility by applying to the characteristics of EPIC architectures, a new register allocation algorithm is proposed. And we proves that proposed register allocation algorithm is more efficient scheme than the conventional scheme when predicated execution is applied to our scheme by experiments. In experimental results, it shows much more performance enhancement, about 19% in proposed scheme than the conventional scheme. So, our scheme is verified that it is an effective register allocation method.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1275-1283
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• 1999

본 논문은 CMOS 디지털 회로에서의 전력 소모의 주원인인 신호의 천이중에서 회로의 동작에 직접적인 영향을 미치지 않는 불필요한 신호의 천이인 글리치를 줄이기 위한 효율적인 알고리즘을 제시한다. 제안된 알고리즘은 회로의 지연 증가 없이 게이트 사이징과 버퍼 삽입에 의해 경로 균등(path balancing)을 이룸으로써 글리치를 감소시킨다. 경로 균등화를 위하여 먼저 게이트 사이징을 통해 글리치의 감소와 동시에, 게이트 크기의 최적화를 통해 회로 전체의 캐패시턴스까지 줄일 수 있으며, 게이트 사이징 만으로 경로 균등화가 이루어지지 않을 경우 버퍼 삽입으로 경로 균등화를 이루게 된다. 버퍼 자체에 의한 전력 소모 증가보다 글리치 감소에 의한 전력 감소가 큰 버퍼를 선택하여 삽입한다. 이때 버퍼 삽입에 의한 전력 감소는 다른 버퍼의 삽입 상태에 따라 크게 달라질 수 있어 ILP (Integer Linear Program)를 이용하여 적은 버퍼 삽입으로 전력 감소를 최대화 할 수 있는 저전력 설계 시스템을 구현하였다. 제안된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 회로의 지연 증가 없이 평균적으로 30.4%의 전력 감소를 얻을 수 있었다.Abstract This paper presents an efficient algorithm for reducing glitches caused by spurious transitions in CMOS logic circuits. The proposed algorithm reduces glitches by achieving path balancing through gate sizing and buffer insertion. The gate sizing technique reduces not only glitches but also effective capacitance in the circuit. In the proposed algorithm, the buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the additional power consumed by the inserted buffers. To determine the location of buffer insertion, ILP (Integer Linear Program) has been employed in the proposed system. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show an average of 30.4% power reduction.

• The Transactions of the Korea Information Processing Society
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• v.5 no.5
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• pp.1172-1184
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• 1998

ILP(Instruction Level Parallelism) processors use code reordering algorithms to expose parallelism in a given sequential program. When applied to a loop, this algorithm produces a software-pipelined loop. In a software-pipelined loop, each iteration contains a sequence of parallel instructions that are composed of data-independent instructions collected across from several iterations. For vector loops, however the software pipelining technique can not expose the maximum parallelism because it schedules the program based only on data-dependencies. This paper proposes to schedule differently for vector loops. We develop an algorithm to detect vector loops at object code level and suggest a new vector scheduling algorithm for them. Our vector scheduling improves the performance because it can schedule not only based on data-dependencies but on loop structure or iteration conditions at the object code level. We compare the resulting schedules with those by software-pipelining techniques in the aspect of performance.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.1
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• pp.87-92
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• 2002

Placement is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to optimize the circuit performance. The most popular algorithms for placement include the cluster growth, simulated annealing and integer linear programming. In this paper we propose a stochastic evolution algorithm searching solution space for the placement problem, and then compare it with simulated annealing by analyzing the results of each implementation.

• Journal of the Korea Society of Computer and Information
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• v.7 no.3
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• pp.42-48
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• 2002

Placement is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to optimize the circuit performance. The most popular algorithms for placement include the cluster growth, simulated annealing and integer linear programming. In this paper we propose a genetic algorithm searching solution space for the placement problem, and then compare it with simulated annealing by analyzing the results of each implementation.

• The Journal of the Korea Contents Association
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• v.7 no.12
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• pp.262-272
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• 2007

SAD (Sum of Absolute Difference) algorithm is the most frequently executing routine in motion estimation, which is the most demanding process in motion picture encoding. To enhance the performance of motion picture encoding on a VLIW processor, an optimal implementation of SAD algorithm on VLIW processor should be accomplished. In this paper, we propose an implementation of optimal scheduling of SAD algorithm with conditional branch on a VLIW-based high performance DSP. We first transform the nested loop with conditional branch of SAD algorithm into a single loop with conditional branch which has a large enough loop body to utilize fully the ILP capability of VLIW DSP and has a conditional branch to make the escape from loop to be achieved as soon as possible. And then we apply a modulo scheduling technique to the transformed single loop. We test the proposed implementation on TMS320C6713, and analyze the code size and performance with respect to processing time. Through experiments, it is shown that the SAD implementation proposed in this paper has small code size appropriate for embedded applications, and the H.263 encoder with the proposed SAD implementation performs better than other H.263 encoder with other SAD implementations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.66-77
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• 2000

This paper presents a fast partitioning heuristic for hardware/software codesign called Best Imaginary Level-Iterative(BILI) partitioning which iteratively applies BIL heterogeneous multiprocessor scheduling heuristic to minimize the cost within the given time constraint. The proposed algorithm solves the partitioning problem with the implementation bin selection problem as well as architectures with multiple software modules. It costs about 15% less than the GCLP and at most about 5% more than the optimal solution obtained by the Integer Linear Programming(ILP) algorithm.

• Journal of Korean Institute of Industrial Engineers
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• v.23 no.2
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• pp.323-341
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• 1997

Traditionally, the Process Planning problems and the Scheduling problems have been considered as independent ones. However, we can take much advantages by solving the two problems simultaneously. In this paper, we deal with the enlarged problem that takes into account both the process planning and the scheduling problems. And we present a solution algorithm for the problem assuming that the given process plan data is represented by AND/OR graph. A mathematical model(mixed ILP model) whose objective is the minimization of the makespan, is formulated. We found that we can get the optimal solutions of the small-size problems within reasonable time limits, but not the large-size problems. So we devised an algorithm based on the decomposition strategy to solve the large-scale problems (realistic problems) within practical time limits.