• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.3-4
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• 2006

In this paper, a nickel silicide technology with post-silicidation annealing effect for thin film SOI devices is investigated in detail. Although lower resistivity Ni silicide can be easily obtained at low forming temperature, poor thermal stability and changing of characteristic are serious problems during the post silicidation annealing like ILD (Inter Layer Dielectric) deposition or metallization. So these effects are observed as deposited Ni thickness differently on As doped SOI (Si film 30nm). Especially, the sheet resistance of Ni thickness deposited 20nm was lower than 30nm before the post silicidation annealing. But after the post silicidation annealing, the sheet resistance was changed. Therefore, in thin film SOI MOSFETs or Ni-FUSI technology that the Si film is less than 50nm, it is important to decide the thickness of deposited Ni in order to avoid forming high resistivity silicide.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.1-8
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• 2006

In this paper, reliability (HCI, NBTI) and device performance of nano-scale CMOSFETs with different channel stress were investigated. It was shown that NMOS and PMOS performances were improved by tensile and compressive stress, respectively, as well known. It is shown that improved device performance is attributed to the increased mobility of electrons or holes in the channel region. However, reliability characteristics showed different dependence on the channel stress. Both of NMOS and PMOS showed improved hot carrier lifetime for compressive channel stress. NBTI of PMOS also showed improvement for compressive stress. It is shown that $N_{it}$ generation at the interface of $Si/SiO_2$ has a great effect on the reliability. It is also shown that generation of positive fixed charge has an effect in the NBTI. Therefore, reliability as well as device performance should be considered in developing strained-silicon MOSFET.

• Journal of the Korean Vacuum Society
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• v.7 no.4
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• pp.368-373
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• 1998

As device dimensions approach submicrometer size in ULSI, the demand for interlayer dielectric materials with very low dielectric constant is increased to solve problems of RC delay caused by increase in parasitic resistance and capacitance in multilevel interconnectins. Fluorinated amorphous carbon in one of the promising materials in ULSI for the interlayer dielectric films with low dielectric constant. However, poor thermal stability and adhesion with Si substrates have inhibited its use. Recently, amorphous hydrogenated carbon (a-C:H) film as a buffer layer between the Si substrate and a-C:F has been introduced because it improves the adhesion with Si substrate. In this study, therfore, a-C:F/a-C:H films were deposited on p-type Si(100) by ECRCVD from $C_2F_6, CH_4$and $H_2$gas source and investigated the effect of forward power and composition on the thickness, chemical bonding state, dielectric constant, surface morphology and roughness of a-C:F films as an interlayer dielectric for ULSI. SEM, FT-IR, XPS, C-V meter and AFM were used for determination of each properties. The dielectric constant in the a-C:F/a-C:H films were found to decrease with increasing fluorine content. However, the dielectric constant increased after furnace annealing in $N_2$atomosphere at $400^{\circ}C$ for 1hour due to decreasing of flurorine content. However, the dielectric constant increased after furnace annealing in $N_2$atmosphere at $400^{\circ}C$ for 1hour due to decreasing of fluorine concentration.