• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.23-29
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• 2011

A dB-linearity improved variable gain amplifier (VGA) for GPS receiver is presented. The Proposed dB-linear current generator has improved dB-linearity error of ${\pm}0.15$dB. The VGA for GPS is designed using proposed dB-linear current generator and composed of 3 stage amplifiers. The IF frequency is assumed as 4MHz and the linearity requirement of the VGA for GPS receiver is defined as 24dBm of IIP3 using cascaded IIP3 equation and the VGA satisfies 24dBm when minimum gain mode. The DC-offset voltage is eliminated using DC-offset cancelation loop. The gain range is from -8dB to 52dB and the dB-linearity error satisfies ${\pm}0.2$dB. The 3-dB frequency has range of 35MHz~106MHz for the gain range. The VGA is designed using 0.18${\mu}m$ CMOS process. The power consumption is 3mW with 1.8V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.638-646
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• 2005

In recent wireless communications, direct conversion transceiver or If sampling SDR-based receivers have being designed as an alternative to conventional transceiver topologies. In direct conversion receiver a.chitectu.e, the 1.equency/phase offset between the RF input signal and the local oscillator signal is a major impairment factor even though the conventional AFC/APC compensates the service deterioration due to the offset. To rover the limited tracking range of the conventional method and effectively aid compensation scheme in terms of I/Q channel imbalances, the frequency/phase offset compensation in RF-front end signal stage is proposed in this paper. In RF-front end, the varying phase offset besides the fixed large frequency/phase offset are corrected by using early-late phase compensator. A more simple frequency and phase tacking function in digital signal processing stage of direct conversion receiver is effectively available by an ingenious frequency/phase offset tracking method in RF front-end stage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.3
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• pp.345-353
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• 2011

An 1.485 Gbit/s video signal transmission system using the carrier frequency of H-band(220~325 GHz) was implemented and demonstrated for the first in domestic. The RF front-end was composed of Schottky barrier diode sub-harmonic mixers(SHM) and frequency triplers, and diagonal horn antennas for transmitter and receiver, respectively. The transmitted carrier frequency of 246 GHz was implemented in the H-band, and LO frequencies of H-band SHM is 120 GHz and 126 GHz for transmit and receive chains, respectively. The modulation scheme is ASK(Amplitude Shift Keying) where IF frequency is 5.94 GHz and the envelop detection was used in heterodyne receiver architecture, and direct detection receiver using ZBD(Zero Bias Detector) was implemented as well. The 1.485 Gbit/s video signal with HD-SDI format was successfully transmitted over wireless link distance of 5 m and displayed on HDTV at the transmitted average output power of 20 ${\mu}W$.

• Journal of Ocean Engineering and Technology
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• v.24 no.1
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• pp.166-171
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• 2010

In this paper, the front-end of a digital receiver with a 25 kHz carrier frequency, 5 kHz symbol rate, and any excess-bandwidth is designed using two basic facts. The first is known as the uniform sampling theorem, which states that the sampled sequence might not suffer from aliasing even if its sampling rate is lower than the Nyquist sampling rate if the analog signal is a bandpass one. The other fact is that if the sampling rate is 4 times the center frequency of the sampled sequence, the front-end processing complexity can be dramatically reduced due to the half of the sampled sequence to be multiplied by zero in the demixing process. Furthermore, the designed front-end is simplified by introducing sub-filters and sub-sampling sequences. The designed front-end is composed of an A/D converter, which takes samples of a bandpass filtered signal at a 20 kHz rate; a serial-to-parallel converter, which converts a sampled bandpass sequence to 4 parallel sub-sample sequences; 4 sub-filter blocks, which act as a frequency shifter and lowpass filter for a complex sequence; 4 synchronized switches; and 2 adders. The designed front-end dramatically reduces the computational complexity by more than 50% for frequency shifting and lowpass filtering operations since a conventional front-end requires a frequency shifting and two lowpass filtering operations to get one lowpass complex sample, while the proposed front-end requires only four filtering operation to get four lowpass complex samples, which is equivalent to one filtering operation for one sample.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.469-472
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• 2008

In this paper, we discuss the recent trends on the passive UHF RFID tag chip design techniques and several important system parameters. We also summarize link budget studies on both conventional and modem UHF RFID communications. The paper highlights the reverse link limited case, which has known to be the minor concern if reader continuous wave (CW) can reach the tag in sufficient level. This makes sense when the tag sensitivity is rather high (over 10-12${\mu}W$); however, since the tag chip fabrication technologies have been developed by time, the tag chip threshold levels are now less-dominant in determining link margin. If the tag limitation can be alleviated, the forward link limited case can be resolved; thus, we rather focus on the path-loss problem. Since the path-losses are still exist in both forward and reverse links, and it can be doubled while CW travels the reader-tag-reader path because forward link and reverse link are on the same distance. Consider if reader receiver sensitivity is very high in the worst case. In this case, weaken tag response (i.e., backscatters) cannot reach the level that reader receiver can process tag data; bit-error rate can be higher. Overall, backscatter levels should be high enough so that reader receiver can correctly function. After discussing link budget, we carried out practical measurements on fading effects between two circularly polarized UHF RFID antennas in a small scale area.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.987-993
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• 2013

Chaos communication system has characteristics of non-periodic, non-predictability, broadband signal and easy implementation. Also, chaos communication system is sensitive to the initial value, because completely another signal is generated when initial value of chaos equation is changed subtly. By these characteristics, security of chaos communication system is generally evaluated better than other digital communication systems. However, BER(Bit Error Rate) performance is worse than other digital communication systems, because transmitter and receiver of existing chaos communication system are strongly influenced by reference signal and noise. So, studies in order to improve the BER performance of chaos communication system is continuously performed. In this paper, We will propose a new CDSK (Correlation Delay Shift Keying) receiver in order to improve the BER performance. After we compare to the performance of existing receiver and proposed receiver, BER performance of proposed receiver evaluate. A novel receiver has characteristic that BER performance is better than existing receiver. However, if existing transmitter is used, existing receiver is possible to recover information bits even though BER performance is bad. Therefore, we propose a novel CDSK transmitter in order to improve the security of proposed receiver. When information bits are transmitted by using proposed transmitter, existing receiver is impossible to recover information bits, and proposed receiver is possible to recover information bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1423-1430
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• 2016

The MAC protocols, which are classified into synchronous and asynchronous MAC protocol in the wireless sensor network, have actively studied. Especially, the asynchronous MAC protocol needs to research on the algorithm synchronizing between nodes, since each node independently operates in its own duty cycle. Typically, Receiver-Initiated MAC protocol is the algorithm synchronizing particular nodes by using beacon immediately transmitted by each node when it wakes up. However, the sender consumes unnecessary energy because it blankly waits until receiving the receiver's beacon, even if it does not know when the receiver's beacon is transmitted. In this paper, we propose the MAC protocol which can improve the performance by selecting an optimal node between a sender and a receiver to overcome the disadvantages. The simulation results show that the proposed algorithm improves energy efficiency and decreases average delay time than the conventional algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4B
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• pp.308-315
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• 2002

This paper proposes new probability models for wideband code division multiple access (W-CDMA) signals. The performance of a W-CDMA system is evaluated by calculating the average bit error rate(BER) which is derived from the probability distribution of the W-CDMA receiver output. If a probability model of the receiver output is available, the performance evaluation becomes much simpler and it enables diverse analyses of the system for channel coding and other purposes. In this paper, probability distributions of W-CDMA signals, more specifically those of the receiver output, are represented as Rayleigh and noncentral chi distribution, considering various bandwidths and channel environments. The adequacy of a probability model is verified by chi-square test of 1% significance level. The BER of the system obtained from the simulation results is compared to that obtained from the probability model to demonstrate the usefulness of the proposed models.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.784-789
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• 2007

This paper presents an implementation of a new type of architecture to improve an overflow problem on the network buffer. Each receiver channel of network system stores the message in its own buffer. If some receiver channel receives many messages, buffer overflow problem may occur for the channel. This paper proposes a network controller that implements a receiver channel with shared-memory to save all of the received messages from the every incomming channels. The proposed architecture is applied to ARINC-429, a real-time control network for commercial avionics system. For verifying performance of the architecture, ARINC-429 controller is designed using a SOPC platform, designed by Verilog and targeted to Xilinx Virtex-4 with a built-in PPC405 core.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1354-1357
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• 2002

In this paper, we propose a suboptimal receiver combining adaptive array antenna and orthogonal decision-feedback detector in DS/CDMA system. Adaptive array antenna can cancel out undesired signal using beamforming scheme. However, if there are interfering signals from undesired users with the same incident angle as that of a desired user, an adaptive array antenna cannot suppress them. The proposed receiver can cancel out remaining interference from users having nearly the same beam pattern. And we employ Orthogonal Decision-Feedback Detector (ODFD) as multiuser detection. The ODFD performs as good as the decorrelating decision -feedback detector (DDD) with much less complexity. Simulation results show that the proposed system provides a significantly enhanced performance.