• Title/Summary/Keyword: IF receiver

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W-band Single-chip Receiver MMIC for FMCW Radar (FMCW 레이더용 W-대역 단일칩 수신기 MMIC)

  • Lee, Seokchul;Kim, Youngmin;Lee, Sangho;Lee, Kihong;Kim, Wansik;Jeong, Jinho;Kwon, Youngwoo
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.10
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    • pp.159-168
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    • 2012
  • In this paper, a W-band single-chip receiver MMIC for FMCW(Frequency-modulated continuous-wave) radar is presented using $0.15{\mu}m$ GaAs pHEMT technology. The receiver MMIC consists of a 4-stage low noise amplifier(LNA), a down-converting mixer and a 3-stage LO buffer amplifier. The LNA is designed to exhibit a low noise figure and high linearity. A resistive mixer is adopted as a down-converting mixer in order to obtain high linearity and low noise performance at low IF. An additional LO buffer amplifier is also demonstrated to reduce the required LO power of the W-band mixer. The fabricated W-band single-chip receiver MMIC shows an excellent performance such as a conversion gain of 6.2 dB, a noise figure of 5.0 dB and input 1-dB compression point($P_{1dB,in}$) of -12.8 dBm, at the RF frequency of $f_0$ GHz, LO input power of -1 dBm and IF frequency of 100 MHz.

A High Swing Range, High Bandwidth CMOS PGA and ADC for IF QPSK Receiver Using 1.8V Supply

  • Lee, Woo-Yol;Lim, Jong-Chul;Park, Hee-Won;Hong, Kuk-Tae;Lee, Hyeong-Soo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.4
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    • pp.276-281
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    • 2005
  • This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.

A Study on Interference Cancelling Receiver with Adaptive Blind CMA Array (적응 블라인드 CMA 어레이를 이용한 간섭 제거 수신기에 관한 연구)

  • 우대호;변윤식
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.4A
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    • pp.330-335
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    • 2002
  • In the direct sequence code division multiple access system, the problem of multiple access interference due to multiple access is generated. A interference cancelling receiver is used to solve this problem. The conventional interference cancelling receiver is structure of successive interference canceller using antenna array. In this structure, the difference of between method I and method II depends on updating weight vector. In this paper, the adaptive blind CMA array interference cancelling receiver using cost function of constant modulus algorithms is proposed to update weight vector at conventional structure. The simulation compared the proposed interference cancelling receiver with two conventional interference cancelling receivers by signal to interference ratio and bit error rate curve under additive white Gaussian noise environment. The simulation results show that the proposed receiver has about the gain of SIR of 1.5[dB] more than method I which is conventional receiver at SIR curve, and about the gain of SIR of 0.5(dB) more than method II. In BER curve, the proposed IC receiver about the gain of SNR of 2[dB] more than method I and about the gain of SNR of 0.5[dB] more than method If, Thus, the proposed interference cancelling receiver has the higher performance than conventional interference cancelling receivers.

A Fast and Precise Blind I/Q Mismatch Compensation for Image Rejection in Direct-Conversion Receiver

  • Kim, Suna;Yoon, Dae-Young;Park, Hyung Chul;Yoon, Giwan;Lee, Sang-Gug
    • ETRI Journal
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    • v.36 no.1
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    • pp.12-21
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    • 2014
  • In this paper, we propose a new digital blind in-phase/quadrature-phase (I/Q) mismatch compensation technique for image rejection in a direct-conversion receiver (DCR). The proposed image-rejection circuit adopts DC offset cancellation and a sign-sign least mean squares (LMS) algorithm with a unique step size adaptation both for a fast and precise I/Q mismatch estimation. In addition, several performance-optimizing design considerations related to accuracy, speed, and hardware simplicity are discussed. The implementation of the proposed circuit in an FPGA results in an image-rejection ratio (IRR) of 65 dB, which is the best performance with modulated signals, along with an adaptation time of 0.9 seconds, which is a tenfold increase in the compensation speed as compared to previously reported circuits. The proposed technique will be a promising solution in the area of image rejection to increase both the speed and accuracy of future DCRs.

A Method of Improving Isolation Between Tx and Rx Paths in TDD Systems (TDD 시스템에서 송수신 격리도 향상 방법)

  • Kang, Sang-Gee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.1
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    • pp.17-22
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    • 2009
  • A switch or circulator is used for distinguishing between the paths of transmitter and receiver in TDD systems. If the isolation between Tx and Rx paths is low in TDD systems, the output signal of the ransmitter acts as an interferer to the receiver even if the transceiver operates on the receiver mode. In this paper we propose a method to get high isolation characteristics between transmitting and receiving paths in TDD systems. We implement the module with a proposed improving method to verify the effect of the isolation improvement and the experimental results are presented. The isolation improvement of above 44.8 dB over the frequency bandwidth of 30 MHz is obtained from the implemented isolation improvement module.

A Dual-Band Through-the-Wall Imaging Radar Receiver Using a Reconfigurable High-Pass Filter

  • Kim, Duksoo;Kim, Byungjoon;Nam, Sangwook
    • Journal of electromagnetic engineering and science
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    • v.16 no.3
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    • pp.164-168
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    • 2016
  • A dual-band through-the-wall imaging radar receiver for a frequency-modulated continuous-wave radar system was designed and fabricated. The operating frequency bands of the receiver are S-band (2-4 GHz) and X-band (8-12 GHz). If the target is behind a wall, wall-reflected waves are rejected by a reconfigurable $G_m-C$ high-pass filter. The filter is designed using a high-order admittance synthesis method, and consists of transconductor circuits and capacitors. The cutoff frequency of the filter can be tuned by changing the reference current. The receiver system is fabricated on a printed circuit board using commercial devices. Measurements show 44.3 dB gain and 3.7 dB noise figure for the S-band input, and 58 dB gain and 3.02 dB noise figure for the X-band input. The cutoff frequency of the filter can be tuned from 0.7 MHz to 2.4 MHz.

Design and analysis of OFDM receiver employing LMLE algorithm (LMLE 알고리듬을 이용한 OFDM 수신기 설계 및 분석)

  • 이종열;정영모;이상욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.12
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    • pp.3174-3182
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    • 1996
  • In this paper, a new receiver is proposed for the detection of the OFDM(orthogonal frequency division multiplexing) signals in the time-selective multipath fading channel. For the optimal detection, we estimate the transmitted symbols from OFDM demultiplexing signal using the LMLE(linear masimum likelihold estimation) algorithm. Also, in this paper, the lowerbound for BER(bit error rate) using Taylor series approximation is provided. If the matched filter is used for the OFDM receiver in the time-selectivemultipath fading channel, it is known that the SER(symbol error rate) is always greater than $10^{-1}$, due to the cross-talk between adjacent channels. But, the proposed receiver provides of SER with 15dB SNR. Also, it is found that for the receiver implemented using the LMLE algorithm, the performance is shown to be not affected by the increase of th enumber of subchannel and channel path.

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Performance of Energy Detection Spectrum Sensing with Delay Diversity for Cognitive Radio System

  • Kim, Eun-Cheol;Koo, Sung-Wan;Kim, Jin-Young
    • Journal of electromagnetic engineering and science
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    • v.9 no.4
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    • pp.194-201
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    • 2009
  • In this paper, a new spectrum sensing method based on energy detection is proposed and analyzed in a cognitive radio(CR) system. We employ a delay diversity receiver for sensing the primary user's spectrum with reasonable cost and complexity. Conventional CR with the receiver equipping multiple antennas requires additional hardware and space for installing multiple antennas in accordance with increase in the number of antennas. If the number of antennas increases, detection probability as well as hardware complexity and cost rise. Then, it is difficult to make a primary user detector practically. Therefore, we adopt a delay diversity receiver for solving problems of the conventional spectrum detector utilizing multiple antennas. We derive analytical expressions for the spectrum sensing performance of the proposed system. From the simulation results, it is demonstrated that the primary user detector with the delay diversity receiver has almost half the complexity and shows similar or improved performance as compared with that employing multiple antennas. Therefore, the proposed spectrum sensing structure can be a practical solution for enhancing the detection capacity in CR system operations. The results of this paper can be applied to legacy CR systems with simple modifications.

A Two-antenna GPS Receiver Integrated with Dead Reckoning Sensors (Two-antenna 자세 결정용 GPS 수신기와 DR 센서의 통합 시스템)

  • 이재호;서홍석;성태경;박찬식;이상정
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.186-186
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    • 2000
  • In the GPS/DR integrated system, the GPS position(or velocity) is used to compensate the DR output and to calibrate errors in the DR sensor. This synergistic relationship ensures that the calibrated DR accuracy can be maintained even when the GPS signal is blocked. Because of the observability problem, however, the DR sensors are not sufficiently calibrated when the vehicle speed is low. This problem can be solved if we use a multi-antenna GPS receiver for attitude determination instead of conventional one. This paper designs a two-antenna GPS receiver integrated with DR sensors. The proposed integration system has three remarkable features. First, the DR sensor can be calibrated regardless of the vehicle speed with the aid of two-antenna GPS receiver. Secondly, the search space of integer ambiguities in GPS carrier-phase measurements is reduced to a part of the surface of the sphere using DR heading. Thirdly, the detection resolution of cycle-slips in GPS carrier-phase measurements is improved with the aid of DR heading. From the experimental result, it is shown that the search grace is drastically reduced to about 3120 of the non-aided case and the cycle-slips of 1 or half cycle can be detected.

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A Study on the Analysis of Minimum Performance and Design for Receiver System in W-CDMA Handset (W-CDMA 단말기 수신 시스템에서 요구하는 최소성능 분석 및 설계에 관한 연구)

  • Kwack, Jun-Ho;Yun, Seok-Chul;Kim, Hak-Sun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.9A
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    • pp.1005-1012
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    • 2004
  • In this paper, we have analyzed minimum performance required for W-CDMA Handset from standard and Implemented the receiver for W -COMA Handset. We have derived the noise figure and IIP3 of receiver and determined the selectivity about adjacent channel and minimum performance for front-end stage. Before the Implementation, we have verified the performance using AOS simulator In conclusion, we have implemented the receiver for W-COMA Handset using the heterodyne architecture and performed measurement. Therefore, this paper wlll gIVe a guideline for design of the W -COMA Handset.