• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.333-336
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• 2000

Modem standard CMOS process technology suffer from so large amount of PVT i.e process, voltage and temperature variation over 30% of its desired value that accurate resistor value is hard to be achieved. A filter using switched-capacitor(SC) circuit has a time constant proportional to relative capacitor area ratio rather than its absolute value. If the PLL's loop filter were made out of SC circuit, there could be much less PVT variation problem. Furthermore, programmability on the loop filter can be achieved In this paper, we present the PLL with SC loop filter. The accuracy provided by SC filter would be helpful to enhance PLL's locking behaviour.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.5
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• pp.775-784
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• 2010

In this paper we propose a design method of X band frequency hopping synthesizer in terms of phase noise and settling time with DDS driven PLL architecture, which has the advantages of high frequency resolution, fast settling time and small size. In addition, a noble method is proposed to remove the synthesizer output spurious signals due to superposition effect of DDS. The spurious signal which depend on its normalized frequency of DDS, can be dominant if they occur within the PLL loop bandwidth. We verify that the sources of that spurious signals are quasi-amplitude modulation and superposition effect, and suggest that such signals can be eliminated by intentionally creating frequency errors in the developed synthesizer.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.73-81
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• 1994

It is AGC(Automatic Gain Control) amplifier to decide characteristics of IF(Intermediate Frequency) processing IC. When demodulated IF signal by PLL type demodulator, the amplitude of input singla should be maintained at a certain amplitude. The AGC amplifier is an important factor to achieve this condition. The AGC amplifier needs the wide dynamic range, the wide AGC range and better noise characteristics. We designed the AGC amplifier to satisfy these characteristics.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.6
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• pp.286-295
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• 2006

This paper presents a design of a real-time software GPS receiver which runs on a PC. The software GPS receiver has advantages over conventional hardware based receivers in terms of flexibility and efficiency in application oriented system design and modification. In odor to reduce the processing time of the software operations in the receiver, a shared memory structure is used with a dynamic data control, and the byte-type IF data is processed through an Open Multi-Processing technique in the mixer and integrator which requires the most computational load. A high speed data acquisition device is used to capture the incoming high-rate IF signals. The FFT-IFFT correlation technique is used for initial acquisition and FLL assisted PLL is used for carrier tracking. All software modules are operated in sequence and are synchronized with pre-defined time scheduling. The performance of the designed software GPS receiver is evaluated by running it in real-time using the real GPS signals.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.1
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• pp.55-63
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• 2013

Digital retrodirective antenna system is easy to modify and upgrade because it can control the phase information of the output signal toward opposite direction to input signal without a priori knowledge of the arrival direction. Due to this advantage, it is possible to do fast beam tracking. Especially, we need to design the digital PLL performance for the digital retrodirective array antenna system. So, in this paper the settling time of phase estimator and BER performance of retrodirective antenna system are investigated according to design of filter in digital PLL. When QAM signal is used for 1 Mbps with $30^{\circ}$ of phase delay, simulation results show that digital phase conjugation technique has better BER performance by about 1 dB than non-phase conjugation system when digital filter is stable. If not, the system can't estimate the exact phase because of oscillation of filter.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.598-603
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• 1990

This study evaluates the performance of an optical receiver for binary phase shift keying (BPSK) signals in the presence of short noise originating from the photo diode and phase noise of the optical source. The case of using I.O. hybrid compare with the fiber optic hybrid to mix received optical signal and laser local oscillator signal. The impact of these noise is minimized if loop natural frequency and power split ratio between data and carrier recovery branch are choosen optimally. Then it is obtained that required laser linewidt to achieve a BER of 10**-9. The results are the same except theat in case of using the fiber optic hybrid the required optical power is twice as much as the I.O. hybrid.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.77-79
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• 2007

The phase angle of the utility voltage is used in current control of grid-tied fuel cell power converter. Therefore if the detection of phase angle is a problem, Current control is affected by the distorted phase angle. This paper presents a problem of synchronous reference frame PLL algorithm for single-phase systems and proposes compensated synchronous reference frame PLL algorithm. The proposed method helps power quality improvement of grid-tied fuel cell power converter under distorted utility conditions. Simulation and experimental results are presented to demonstrate the validity of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.100-105
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• 2010

In this paper, a FM radio receiver integrated circuit has been developed based on $0.5{\mu}m$ CMOS process for Zero-Crossing FM demodulator over the 88MHz to 108MHz band. The receiver is designed with the low-IF architecture, and includes Low Noise Amplifier(LNA), Down-Conversion Mixer, Phase Locked Loop(PLL), IF LPF, and a comparator. The measured results of the LNA and Mixer show that the conversion gain of 23.2 dB, the input PldB of -14 dBm, and the noise figure of 15 dB. The measured analog block of the LPF and comparator show the voltage gain of over 89 dB, and the IF LPF can configure the passband from 600KHz to 1.3MHz with 100KHz step through the internal control register banks. The designed FM radio receiver operates at 4.5V with the total current consumption of 15.3mA, so the total power consumption is about 68.85mW. The commercial FM radio has been successfully received.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.116-122
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• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.