• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.871-874
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• 1998

A new transmission line parameter extraction method of iC interconnects on silicon substrate is presented. To extract the acurate parameters, the silicon substrate effects were taken into account. Since the electromagnetic fields under the silicon substrate are propagated with slow wave mode, effective dielectric constant and different ground plane with the multi-layer dielectric structures were employed for inductance and capacitance matrix determination. Then accurate signal transients simulation were performed with HSPICE by using the parameters. It was shown that the simulation resutls has an excellent agreement with TDR/TDT measurements.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.59-63
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• 2013

In this paper, the impact of the copper densities of substrate layers on IC package warpage is studied experimentally and numerically. The substrate strips used in this study contained two metal layers, with the metal densities and patterns of these two layers varied to determine their impacts. Eight legs of substrate strips were prepared. Leg 1 to leg 5 were prepared with a HD (high density) type of strip and leg 6 to leg 8 were prepared with UHD (ultra high density) type of strip. The top copper metal layer was designed to feature meshed patterns and the bottom copper layer was designed to feature circular patterns. In order to consider the process factors, the warpage of the substrate bottom was measured step by step with the following manufacturing process: (a) bare substrate, (b) die attach, (c) applying mold compound (d) and post reflow. Furthermore, after the post reflow step, the substrate strips were diced to obtain unit packages and the warpage of the unit packages was measured to check the warpage trends and differences. The experimental results showed that the warpage trend is related to the copper densities. In addition to the experiments, a Finite Element Modeling (FEM) was used to simulate the warpage. The nonlinear material properties of mold compound, die attach, solder mask, and substrate core were included in the simulation. Through experiment and simulation, some observations were concluded.

• Laser Solutions
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• v.15 no.3
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• pp.7-10
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• 2012

Dimensions (line/space) of circuits in IC substrates for high-end chips (e.g. CPU, etc.) are anticipated to decrease as small as $10{\mu}m/10{\mu}m$ in 2014. Since current etch-based circuit-patterning processes are not able to address the urgent requirement from industry, laser-based circuit patterning processes are under active research in which UV laser is used to engrave embedded circuits patterns into IC substrates. In this paper, we used a nanosecond UV laser to directly fabricate embedded circuit patterns into IC substrates with/without ceramic powders. In experiments, we engraved embedded circuit patterns with dimensions (width/depth) of abut $10{\mu}m/10{\mu}m$ and $6{\mu}m/6{\mu}m$ into the IC substrates. Due to the recoil pressure occurring during ablation, the circuit patterning of the IC substrates with ceramic powders showed the higher ablation rate.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.1
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• pp.8-13
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• 2020

Stress is the main cause of warpage failure of very thin substrates with thickness of several hundred ㎛, such as IC packages. Stress usually results from differences in crystal structures and corresponding thermal expansion coefficients when depositing different substances on a substrate. In this study, the behaviors of stress occurring in substrates were numerically analyzed by the thin-film pattern of the rectangles stacked on the substrates. First, the substrate displacement was obtained and the substrate strain and stress were obtained using it. When the tensile force is concentrated at the edge of the thin film pattern, normal and shear stresses are generated around the edge of the thin film pattern. Normal stress occurs near the edges of the thin film pattern and the vertexes. Shear stress also occurs around the edge of the thin film pattern, but unlike normal stress, it does not appear near the vertexes. It was also confirmed that the magnitude and direction of shear stress are changed around the edge. When edge forces of thin-film pattern are equal, the normal stress was about 10 times larger than the shear stress. This indicates that normal stress is the biggest cause of warpage failure.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.1
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 1998.04b
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• pp.6-6
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• 1998

In 1957, the first magnetic disk drive compatible with a movable head was introduced as an external file memory device for computer system. Since then, magnetic disks have been improved by increasing the recording density, which has brought about the development of a high performance thin film magnetic head. The thin film magnetic head has a magnetic circuit on a ceramic substrate using IC technology. The physical property of the substrate material is very important because it influences the tribology of head/disk interface and also manufacturing process of the head. $Al_{2}O_{3}$-TiC ceramics, so called ALTIC, is known to be one of the best substrate materials which satisfies this property requirement. Even though the head is not in direct contact with the disk, frequent instantaneous contacts are unavoidable due to its high rotating speed and the close gap between them. This may cause damage in the magnetic recording media and, thus, it is very important that the magnetic head has a good wear resistance. $Al_{2}O_{3}$-TiC ceramics has an excellent tribological property in head/disk interface. Manufacturing process of thin film head is similar to that of IC, which requires extremely smooth and flat surface of the substrate. The substrate must be readily sliced into the heads without chipping. $Al_{2}O_{3}$-TiC ceramics has excellent machineability and mechanical properties. $Al_{2}O_{3}$-TiC ceramics was first developed at Nippon Tungsten Co. as cutting tool materials in 1968, which was further developed to be used as the substrate materials for thin film head in collaboration with Sumitomo Special Metals Co., Ltd. in 1981. Today, we supply more than 60% of the substrates for thin film head market in the world. In this paper, we would like to present the sintering process of $Al_{2}O_{3}$-TiC ceramics and its property in detail.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.895-898
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• 1999

Recently, small signal modeling of CMOS device becomes more difficult because the design rule goes into deep submicron. De-embedding of substrate parameters is important in order to use CMOS devices at RF frequencies. In this paper, we suggest a new de-embedding model with refined physical meaning and accuracy. In GaAs IC’s, the substrate is almost an insulator but Si substrate has the semiconducting characteristics. It offers some troubles if it is treated like GaAs substrate. The conducting substrate is modeled with five resistances, which leads to very accurate modeling so long as the pad layout is symmetrical. Frequency range is up to 39㎓ and fitting accuracy is as small as 0.00037 on least square errors.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.21-30
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• 2002

According the difference of flex substrate, (reel tape), there are three kind assembly types of LCD driver IC is COG, TCP and COF, respectively. The TCP is the maturest in these types for stability of raw material supply and other specification. And TCP is the major assembly type of LCD driver IC and the huge demand from Taiwan's large TFT LCD panel house since this spring. But due to its package structure and the raw material applied in this package, there is some limitation in fine pitch application of this package type, (TCP). So, COF will be very potential in compact and portable application comparison with TCP in the future. There are three kinds assembly methods in COF, one is ACF by using the anisotropic conductive film to connect the copper lead of tape and gold bump of IC, another is eutectic bonding by using the thermo-pressure to joint the copper lead of tape and gold bump of IC, and last is NCP by using non-conductive paste to adhere the copper lead of tape and gold bump of IC. To have a global realization, this paper will briefly review the status of Taiwan's large TFT panel house, the internal driver IC design house, and the back-end assembly house in the beginning. The different material property of raw material, PI tape is also compared in the paper. The more detail of three kinds of COF assembly method will be described and compared in this paper.

• Transactions on Electrical and Electronic Materials
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• v.5 no.2
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• pp.41-49
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• 2004

Layer transfer process has emerged as a promising tool in the field of thin silicon solar cell technology. This process can use mono-crystalline silicon as a surface for the epitaxial growth of a thin layer of silicon. It requires some sort of surface conditioning of the substrate due to which the surface become suitable for homo-epitaxy and lift off after solar cell fabrication. The successful reuse of substrate has been reported. The use of the conditioned surface without any kind of epitaxial layer growth is also the issue to be addressed. This review paper basically describes the five most cost effective methods on which works are in progress. Several types of possible problems envisaged by different research groups are also incorporated here with necessary discussion. Work in Korea has already started in this area in collaboration IC Design and Fabrication Centre, Jadavpur University, India and that also has been mentioned.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.31-37
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• 1994

Aluminum films were deposited by the pyrolysis of triisobutylaluminum(TIBA) in a cold wall LPCVD system for the metallization of high level IC. the selectivity on Si/SiO2 substrate and the contact resistance on submicron contacts were investigated. The carbon free aluminum film could be obtained when the aluminum film was deposited at low substrate temperature. Contact resistances of CVD Al/n+ Si contacts whose contact size was 0.5 .mu.m werre as low as 20~40.OMEGA./ea, which is 30~50% of contact resistance obtained by sputtering technique.