• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.76-82
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• 2016

In this paper, we evaluated shielding effectiveness (SE) of carbon nanotube (CNT) film using near field scanning (NFS) in near field analysis. We adopted CNT film with deposit carbon density of 5% and thickness of 1mm for evaluation of shielding characteristic. Using a test coupon analogized to an actual IC package, we measured SE according to measuring position and SE according to distances between the CNT film and the test coupon. As a result, the measured SE in the near field varied with frequency. Especially, the measured electric field SE in the center of the test coupon is better than that of the measured edge point of the test coupon where it is affected by fringing effect. The results show that the measured SE in the near field is affected not only by frequency but also by measurement environment such as position and height of the probe and height of shielding film. In conclusion, we should choose proper methods for SE measurement considering interference distance in the electronic control system because there is little correlation between the proposed evaluation method in the near field and ASTM D 4935-10.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.53-58
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• 2013

An innovative packaging solution, Flip Chip with Copper (Cu) Column bond on lead (BOL) Enhanced Process (fcCuBE$^{(R)}$) delivers a cost effective, high performance packaging solution over typical bond on capture pad (BOC) technology. These advantages include improved routing efficiency on the substrate top layer thus allowing conversion functionality; furthermore, package cost is lowered by means of reduced substrate layer count and removal of solder on pad (SOP). On the other hand, as electronic packaging technology develops to meet the miniaturization trend from consumer demand, reliability testing will become an important issue in advanced technology area. In particular, electromigration (EM) of flip chip bumps is an increasing reliability concern in the manufacturing of integrated circuit (IC) components and electronic systems. This paper presents the results on EM characteristics on BOL and BOC structures under electrical current stressing in order to investigate the comparison between two different typed structures. EM data was collected for over 7000 hours under accelerated conditions (temperatures: $125^{\circ}C$, $135^{\circ}C$, and $150^{\circ}C$ and stress current: 300 mA, 400 mA, and 500 mA). All samples have been tested without any failures, however, we attempted to find morphologies induced by EM effects through cross-sectional analysis and investigated the interfacial reaction characteristics between BOL and BOC structures under current stressing. EM damage was observed at the solder joint of BOC structure but the BOL structure did not show any damage from the effects of EM. The EM data indicates that the fcCuBE$^{(R)}$ BOL Cu column bump provides a significantly better EM reliability.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.59-63
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• 2013

In this paper, the impact of the copper densities of substrate layers on IC package warpage is studied experimentally and numerically. The substrate strips used in this study contained two metal layers, with the metal densities and patterns of these two layers varied to determine their impacts. Eight legs of substrate strips were prepared. Leg 1 to leg 5 were prepared with a HD (high density) type of strip and leg 6 to leg 8 were prepared with UHD (ultra high density) type of strip. The top copper metal layer was designed to feature meshed patterns and the bottom copper layer was designed to feature circular patterns. In order to consider the process factors, the warpage of the substrate bottom was measured step by step with the following manufacturing process: (a) bare substrate, (b) die attach, (c) applying mold compound (d) and post reflow. Furthermore, after the post reflow step, the substrate strips were diced to obtain unit packages and the warpage of the unit packages was measured to check the warpage trends and differences. The experimental results showed that the warpage trend is related to the copper densities. In addition to the experiments, a Finite Element Modeling (FEM) was used to simulate the warpage. The nonlinear material properties of mold compound, die attach, solder mask, and substrate core were included in the simulation. Through experiment and simulation, some observations were concluded.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.22-28
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• 1998

Signal transmission and crosstalk of coupled bondwires buried in plastic packages are analyzed using the Method of Moments and the Fourier Transform algorithm. It is also shown that the quasi-static crosstalk model of SPICE is inappropriate for designing the high-speed plastic packages. Plastic packaging material, increasing the self and mutual capacitances, is found to be helpful for the signal transmission integrity due to the dielectric compensation effect. However, it is also observed that the plastic material increases the crosstalk due to the radiation-enhanced mutual coupling effect. By investigating the geometrical and material dependence of the pulse transmission and crosstalk, it is found that the radiation-enhanced coupling effect is significant for most of typical bondwire geometries and plastic package materials. These calculation results can be effectively used for designing plastic packages of high-speed digital IC's and monolithic RFIC's.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.108-114
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• 2016

This paper presents a 2.6 GHz Doherty power amplifier IC to enhance the back-off efficiency. In order to apply to small-cell base stations, the Doherty power amplifier was fabricated using GaN-HEMT process for high power density. In addition, the implemented Doherty power amplifier was mounted on a QFN package. The implemented GaN-HEMT Doherty power amplifier was measured using LTE downlink signal with 10 MHz bandwidth and 6.5 dB PAPR for verification. A power gain of 15.8 dB, a drain efficiency of 43.0 %, and an ACLR of -30.0 dBc were obtained at an average output power level of 33.9 dBm.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.69-72
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• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• Journal of Nutrition and Health
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• v.30 no.6
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• pp.679-689
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• 1997

Nutrition label (NL) on the package of processed food provides consumers with a reliable and consistent source of information . It has been considered as a useful aid for food selection and a potent educational tool for nutrition in daily life. Since current nutrition labeling regulation in Korea does not define a format for presenting nutrition information a wide variety of NL format exists in the markers created by individual manufacturers. Development of standard NL format and its registration remain to be the work for the professionals and government officials. However the acceptance and evaluation of NL by the consumers is a very important and necessary process in the development of NL formats. In this study four different formats A, B, C, D were formulated based on currently circulating labels and new U.S.NL. Subjects used for evaluation of these formats were middle -aged highly educated housewives, who and the potential users of NL. Major parameters observed through the questionnare were their nutritional knowledge of RDA, ability of IC(Information Comparison) and CA (Comprehension and Application of informed nutrient contents), as well as their preference to the different formats. The results are summarized as follows. 1) Of the 178 subjects , 89.9% of the middleaged housewives were college graduates. Their nutrition knowledge of RDA were relatively satisfactory showing over 80% correlation on the basic concepts and unit while for numerical value less than 50% correct answer. 2) IC test scores were significantly different among the formats showing the highest values for format A and B which are presented as absolute value and % RDA, respectively. Format C presented as serving size(number of products) showed the lowest score. CA scores were also significantly different, though the increased load of information did not facilitate to increase the consumers comprehension. 3) RDA knowledge test scores and the scores of IA and CA were correlated in format A and D but not in format B and C suggesting % RDA presentation would be more acceptable to the less educated group. 4) For the preference in the aspects of easiness and time-saving format A was the best one then format D supporting the result of IC and CA test. The results of the present study indicate the most useful and preferred format is the simplest format presented as absolute value without RDA, . The secondly preferred format is the new NL format of the US with much information .

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.320-330
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• 2012

In this paper, we investigate the power integrity of grid structures for power and ground distribution on printed circuit board (PCB). We propose the 2D transmission line method (TLM)-based model for efficient frequency-dependent impedance characterization and PCB-package-integrated circuit (IC) co-simulation. The model includes an equivalent circuit model of fringing capacitance and probing ports. The accuracy of the proposed grid model is verified with test structure measurements and 3D electromagnetic (EM) simulations. If the grid structures replace the plane structures in PCBs, they should provide effective shielding of the electromagnetic interference in mobile systems. An analytical model to predict the shielding effectiveness (SE) of the grid structures is proposed and verified with EM simulations.