• 대한전자공학회논문지SD
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• 제37권1호
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• pp.60-66
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• 2000

본 논문에서는 자체 테스트기능과 보안기능을 각춘 공중전화 가드 IC를 검증함으로써 향후 공중전화 시스템의 국산화에 응용 가능성을 확인한다. 본 연구에서 설계된 공중전화용 IC는 개의 명령어를 지원하고 금액 등 여러 가지 정보를 저장할 수 있는 비휘발성 메모리를 갖는다. 하나의 직렬 I/O로써 이루어지는 외부와의 통신 때문에 야기되는 테스트 시간 문제를 보완하기 위해 대부분의 테스트가 칩 내부에서 동작하도록 자체 테스트 기능을 추가하였다. 또한 여러 가지 보안기능이 소프트웨어, 하드웨어적으로 구현되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 춘계학술대회 논문집
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• pp.83-84
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• 2009

This paper presents a step-down converter IC for automotive applications. This device was designed for a 40V/1A high-power output for voltage reference of automotive IC. It provides 250kHz PWM(pulse width modulation) and PFM(pulse frequency modulation) according to load conditions. This device was simulated Spectre of IC Design Tool And fabricated Dong-bu Hitec 0.35um BD350BA process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 춘계학술대회 논문집
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• pp.81-82
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• 2009

This paper introduces a gate drive IC for power modules with shoot-through immunity. A new approach uses a bootstrap diode as a high-side voltage bias and a level shift function at the same time. Therefore, the gate drive circuit becomes a simple and low-cost without conventional level shift functions such as HVIC(High-Voltage IC), optocoupler and transformer. The proposed gate drive IC is designed and fabricated using the Dongbu-Hitek's 0.35um BD350BA process. It has been tested and verified with IGBT modules.

• 대한기계학회논문집
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• 제18권10호
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• pp.2606-2615
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• 1994

Sorting time is one of the most important issues for auto IC test handling systems. In actual system, because of too much path, reducing the computing time for finding a sorting path is the key way to enhancing the system performance. The exhaustive path search technique can not be used for real systems. This paper proposes heuristic sorting algorithm to find the minimal sorting time. The suggested algorithm is basically based on the best-first search technique and multi-level search technique. The results are close to the optimal solutions and computing time is greately reduced also. Therefore the proposed algorthm can be effectively used for real-time sorting process in auto IC test handling systems.

• Journal of Power Electronics
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• 제17권5호
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• pp.1372-1381
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• 2017

This paper presents a high-side switch driver IC capable of improving the current sensing accuracy and providing reverse battery protection. Power semiconductor switches used to replace relay switches are encumbered by two disadvantages: they are prone to current sensing errors and they require additional external protection circuits for reverse battery protection. The proposed IC integrates a gate driver and current sensing blocks, thus compensating for these two disadvantages with a single IC. A p-sub-based 90-V $0.13-{\mu}m$ bipolar-CMOS-DMOS (BCD) process is used for the design and fabrication of the proposed IC. The current sensing accuracy (error ${\leq}{\pm}5%$ in the range of 0.1 A-6.5 A) and the reverse battery protection features of the proposed IC were experimentally tested and verified.

• 한국자동차공학회논문집
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• 제16권3호
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• pp.15-22
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• 2008

Applications of bonded dissimilar materials such as integrated circuit(IC) packages, ceramics/metal and resin/metal bonded joints, are very increasing in various industry fields. It is very important to analyze the thermal stress and stress singularity at interface edge in bonded joints of dissimilar materials. In order to investigate the IC package crack propagating from the edge of die pad and resin, the fracture parameters of bonded dissimilar materials and material properties are obtained. In this paper, the thermal stress and its singularity index for the IC package were analyzed using 2-dimensional elastic boundary element method(BEM). From these results, crack propagation direction and path by thermal stress in the IC package were numerically simulated with boundary element method.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2001년도 가을 학술발표논문집 Vol.28 No.2 (2)
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• pp.361-363
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• 2001

반도체 패키지의 마킹검사(marking inspection)를 위해서는 입력 영상으로부터 검사할 패키지의 정확만 위치 검출과 패키지 윗면에 나타난 제작사 로고, 문자, Pin1 딤플의 추출이 필수적이다. 본 연구는 마킹검사를 위한 선행 연구로 마킹검사를 수행할 때, 검사할 IC 패키지의 위치와 방향을 정확하게 검출하는 것을 목적으로 하고 있다. IC 패키지의 외곽을 구성하는 리드의 명도 값은 트레이의 명도 값과 큰 차이를 나타낸다. 그러나 IC 패키지의 방향을 나타내는 Pin1 딤플은 배경과 동일한 색상으로 다만 약간 오목하게 들어가서 명도 값의 차이가 미세하다. 이러한 두 가지 상이한 특징을 효과적으로 처리하기 위하여 적응적 다중 이진화 방법을 제시하였다. 76개의 명도 영상에 대한 실험 결과 제안된 이진화 방법은 매우 효과적이었으며, 이진화된 영상으로부터 IC 패키지의 정확한 위치 검출과 방향 확인이 가능하였다.

• 한국신뢰성학회지:신뢰성응용연구
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• 제7권1호
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• pp.1-11
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• 2007

This paper presents a derating design approach for reliability improvement of a regulator IC. The IC is usually used in SMPS. The main failure mechanism of interest is voltage drop due to the package delamination mainly caused by two stresses, i.e. temperature and current. The lifetime under stresses is modeled as a function of stresses and time using accelerating life testings. Quantitative and qualitative variation in lifetime according to stress variations are investigated using the modeled lifetime. Stress levels would be determined to achieve required reliability levels in the aspect of derating design for reliability.

• Bulletin of the Korean Chemical Society
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• 제24권10호
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• pp.1444-1448
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• 2003

The microsurface adsorption - spectral correction (MSASC) technique has been applied to the interaction of indigo carmine (IC) with cetyltrimethylammonium bromide (CTAB). The aggregation of IC on CTAB obeys Langmuir isothermal adsorption. The results show that both the monomer complex $IC{\cdot}CTAB$ and the micellar complex $(IC{\cdot}CTAB)_{78}$ were formed. The binding constant of the monomer complex was calculated to be $K_{IC{\cdot}CTAB}$ = 2.20 ${\times}10^5L{\cdot}mol^{-1}$, and the molar absorptivity of the micellar complex was calculated to be ${\varepsilon}_{(IC{\cdot}CTAB)78}\;^{560nm}$ = 8.58 ${\times}10^5L{\cdot}mol^{-1}{\cdot}cm^{-1}$. The aggregation was applied to the determination of cationic surfactant in wastewater.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.93-100
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• 2003

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.