• Proceedings of the Korean Magnestics Society Conference
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• 2000.09a
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• pp.5-32
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• 2000

MRAM, High performance MRAM using MTJS demostrated, fully integrated MTJ MRAM with CMOS circuits, write time ~2.3 nsec; read time ~3 nsec, Thermally stable up to ~350 C, Switching field distibution controlled by size & shape. Magnetic Tunnel Junction Properties, Magnetoresistance: ~50% at room temperature, enhanced by thermal treatment, Negative and Positive MR by interface modification, Spin Polarization: >55% at 0.25K, Insensitive ot FM composition, Resistance $\times$ Area product, ranging from ~20 to 10$^{9}$ $\Omega$(${\mu}{\textrm}{m}$)$^{2}$, Spin valve transistor, Tunnel injected spin polarization for "hot" electrons, Decrease of MTJMR at high bias originates from anode.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.200-209
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• 2008

This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-GHz PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dual-path VCO is important for deterministic jitter (DJ) performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.4
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• pp.10-21
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• 2003

Recently, the optical subscriber interface module uses the high performance network processor to quickly develop new application services such as MPLS, VPN, RPR and EPON with a short time-to-market. Although a number of vendors are developing the network processor at 2.5Gbps, only the IBM NP4GS3 can provide packet processing with wire-speed at 2.5Gbps. IBM NP4GS3, however, uses its unique speed DASL interface instead of CSIX-Ll interface, which has standardized by M: Forum currently Therefore, we implement an interconnection mechanism to use the switch fabric with CSIX-Ll interface. In this paper, we suggest the architecture and a packet control mechanism supporting interconnection between IBM NP4GS3 DASL and CSIX-Ll switch interface using the common IBM UDASL ASIC and XILINX FPGA.

• Ceramist
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• v.9 no.4
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• pp.58-71
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• 2006

Scaling of the gate stack has been one of the major contributors to the performance enhancement of CMOSFET devices in past technology generations. The scalability of gate stack has diminished in recent years and alternative gate stack technology such as metal electrode and high-k dielectrics has been intensively studied during the last decade. Tody the performance of high-k dielectrics almost matches that of conventional $SiO_2-based$ gate dielectrics. However, many technical challenges remain to be resolved before alternative gate stacks can be introduced into mainstream technology. This paper reviews the research in alternative gate stack technologies to provide insights for future research.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11b
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• pp.865-868
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• 2003

ESP는 Effective System Performance의 약자로 NERSC에서 개발한 HPC 시스템에 대한 새로운 성능 측정 기준이다. 기존 HPC 시스템에서는 주로 성능 측정의 대상으로 시스템[프로세서]의 계산 성능에 주안점을 두었지만 시스템의 효율성은 무시되는 경향이 있었다. ESP는 실제 운영환경에서 배치 작업 스케줄러 및 병렬 작업 환경에 영향을 받는 시스템 효율성(ESP:Effective System Performance)을 측정하는 데 주안점을 두고 있다. KISTI 슈퍼컴퓨팅센터는 2003년 7월 국내 최고 성능의 슈퍼컴퓨터인 IBM p690+ 시스템의 도입을 완료하고 ESP를 사용하여 배치 작업 스케줄러인 LoadLeveler의 스케줄링 알고리즘에 따른 시스템 효율성 벤치마크를 수행하였다. 이 벤치마크를 통해서 효율적인 시스템 자원 활용을 위한 작업 스케줄링 알고리즘의 적용 근거를 마련하게 되었다.

• 한국IT서비스학회:학술대회논문집
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• 2003.11a
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• pp.44-59
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• 2003

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11a
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• pp.229-232
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• 2002

분간 병렬 시스템에서 사용되는 배치 작업 스케줄링 기법으로 잘 알리진 것은 Gang Scheduling과 Backfilling Scheduler가 있다. 특히 IBM SP 시스템에서 주로 사용되는 작업 스케줄러인 LoadLeveler 최신 버전에서는 이전 버전에서도 지원하였던 Backfilling Scheduler 뿐만 아니라 Gang Scheduling 기법을 새롭게 지원하게 되었다. 이에 따라 KISTI 슈퍼컴퓨팅센터에서는 슈퍼컴퓨터 3호기로 신규 도입된 IBM p690 시스템에서 LoadLeveler의 Gang Scheduling 혹은 Backfilling Scheduler 중의 한 가지 기법을 선택하여 서비스 레벨 클래스를 구현하고자 하였다. 이러한 노력의 일환으로 두 가지 스케줄링 기법을 테스트 및 분석하였다. 이에 따르면 Gang Scheduler가 개념상 여러 가지 장점을 가지므로 Backfilling Scheduler에 비하여 서비스 레벨 클래스 구성에는 용이하지만, 불완전한 구현 및 특히 CPU Utilization이 저하되는 심각한 문제점을 가지고 있었다. 따라서 Backfilling Scheduler를 통한 제한적인 서비스 레벨 클래스를 구성하기로 결론지었다.

• Journal of the Korea Society for Simulation
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• v.7 no.1
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• pp.69-83
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• 1998

In this paper, we present the results of simulation by running parallel VHDL simulation on typical MPP(Massively Parallel Processor) systems such as IBM SP2 and SGI Origin 2000. Parallel simulation uses the synchronous protocol and parallel program is implemented using MPI(Message Passing Interface) based on message passing model, so that it can urn on any parallel programming environment which supports MPI, a standard communication library. And then GVT(Global Virtual Time) computation for parallel simulation is based on the global broadcasting with MPI＿Bcast(), which is a standard function in MPI and piggybacking. Our benchmark exhibits that as size of VHDL grows, the parallel simulation has a better performance compared with the sequential simulation. In addition, we also show the results of comparison between IBM SP2 and SGI Origin 2000 by applying the same application to those indirectly.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.379-386
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• 2004

We designed a portable parallel library HPCL(High Performance Computing Library) with following objectives: (1) to provide a close relationship between the parallel code and the original sequential code that will help future versions of the sequential code and (2) to enhance performance of the parallel code. The library is an interface written in C and Fortran programming languages between MPI(Message Passing Interface) and parallel programs in Fortran. Performance results were determined on clusters of PC's and IBM SP4.

• Journal of the Korean Society of Physical Medicine
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• v.15 no.1
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• pp.11-18
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• 2020

PURPOSE: This study was to investigate examined the differences in the autonomic nervous functions of elite female judo athletes according to their performance by measuring the heart rate variability (HRV). METHODS: Sixteen elite female judo players participated in this study. The participants were divided into a high performance and low performance group according to the results of their competitions. The HRV (mean heart rate, SDNN, RMSSD, TP, LF, HF, LF/HF ratio) was measured in the resting status. A t-test was used to compare the two groups, and bivariate logistic regression analysis was performed to determine the HRV elements that affect performance. The data were analyzed using IBM SPSS Statistics ver. 24.0 (IBM Co., Armonk, NY, USA). RESULTS: The mean heart rate was higher in the high performance group (72.88) than in the low performance group (64.75) (p=.049). The LF/HF ratio was higher in the high performance group (3.43) than in the low performance group (0.83), and the results were significant (p=.038). No HRV elements having a significant effect on the performance were observed. CONCLUSION: This study showed that the activity of the sympathetic nervous system was dominant in the high performance group in the resting status than in the low performance. The high performance group is believed to be in the overtraining status who experience more stress.