• Bulletin of the Korean Chemical Society
• /
• 제35권2호
• /
• pp.494-500
• /
• 2014

Indium-doped zinc oxide nanocrystals (IZO NCs), capped with stearic acid (SA) of different sizes, were synthesized using a hot injection method in a noncoordinating solvent 1-octadecene (ODE). The ligand exchange process was employed to modify the surface of IZO NCs by replacing the longer-chain ligand of stearic acid with the shorter-chain ligand of butylamine (BA). It should be noted that the ligand-exchange percentage was observed to be 75%. The change of particle size, morphology, and crystal structures were obtained using a field emission scanning electron microscope (FE-SEM) and X-ray diffraction pattern results. In our study, the 5 nm and 10 nm IZO NCs capped with stearic acid (SA-IZO) were ligand-exchanged with butylamine (BA), and were then spin-coated on a thermal oxide ($SiO_2$) gate insulator to fabricate a thin film transistor (TFT) device. The films were then annealed at various temperatures: $350^{\circ}C$, $400^{\circ}C$, $500^{\circ}C$, and $600^{\circ}C$. All samples showed semiconducting behavior and exhibited n-channel TFT. Curing temperature dependent on mobility was observed. Interestingly, mobility decreases with the increasing size of NCs from 5 to 10 nm. Miller-Abrahams hopping formalism was employed to explain the hopping mechanism insight our IZO NC films. By focusing on the effect of size, different curing temperatures, electron coupling, tunneling rate, and inter-NC separation, we found that the decrease in electron mobility for larger NCs was due to smaller electronic coupling.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제3권2호
• /
• pp.83-88
• /
• 2003

The reset operation of a CCD image sensor was improved using charge trapping of a MOS structure to realize a loe voltage driving. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2V to 5.5V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with $492(H){\;}{\times}{\;}510(V)$ pixels adopting this structure showed complete reset operation with the driving voltage of 3.0V. The resolution chart taken with the image sensor shows no image flow to the illumination of 30 lux, even in the driving voltage of 3.0V.

• 한국시뮬레이션학회논문지
• /
• 제23권3호
• /
• pp.27-32
• /
• 2014

본 논문에서는, 초고집적 CMOS 회로를 위한 얕은 트랜치 격리로 기존의 수직 구조 보다 개선된 성질을 갖는 새로운 구조를 제안하고자 한다. 이를 위해서 제안한 구조는 회자 모양의 얕은 트랜치 격리 구조이다. 특성 분석은 기존 수직 구조와 제안한 구조에 대해서 전자농도 분포, 열전자 스트레스의 산화막 모양, 전위와 전계 플럭스, 열 손상의 유전 전계와 소자에서 전류-전압 특성을 분석 하고자 한다. 물리적 기본 모델들은 TCAD 툴을 이용하며, 집적화 소자들에 있어서 분석 조건은 주위 조건과 전류와 시간의 인가 스트레스 조건이다. 분석 결과, 얕은 트랜치 격리 구조가 소자의 크기가 감소됨에 따라서 수동적인 전기적 기능이었다. 트랜지스터 응용에서 제안한 회자 구조의 얕은 트랜치 격리 구조가 전기적 특성에서 전위차, 전계, 전자농도 분포가 높게 나타났으며, 활성영역에서 스트레스에 의한 산화막의 영향은 감소되었다. 이 결과 데이터를 바탕으로 소자의 전류-전압 특성 결과 분석도 양호한 특성으로 나타났다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 하계학술대회 논문집
• /
• pp.26-31
• /
• 2002

To realize a high integrated Flash memory utilizing SONOS memory devices, the NOR type 1TC(one Transistor Cell) SONOS Flash arrays are fabricated and characterized. This SONOS Flash arrays with common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cell is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$. To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and Bit line erase method are selected as the write operation and the erase method, respectively. The disturbance characteristics according to the write/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• ETRI Journal
• /
• 제28권2호
• /
• pp.253-256
• /
• 2006

We propose a novel power metal oxide semiconductor field effect transistor (MOSFET) employing a strained-Si channel structure to improve the current drivability and on-resistance characteristic of the high-voltage MOSFET. A 20 nm thick strained-Si low field channel NMOSFET with a $0.75\;{\mu}m$ thick $Si_{0.8}Ge_{0.2}$ buffer layer improved the drive current by 20% with a 25% reduction in on-resistance compared with a conventional Si channel high-voltage NMOSFET, while suppressing the breakdown voltage and subthreshold slope characteristic degradation by 6% and 8%, respectively. Also, the strained-Si high-voltage NMOSFET improved the transconductance by 28% and 52% at the linear and saturation regimes.

• 한국전기전자재료학회논문지
• /
• 제16권5호
• /
• pp.372-377
• /
• 2003

To realize a high integrated flash memory utilizing SONOS memory devices, the NOR type ITC(one Transistor Cell) SONOS flash arrays are fabricated and characterized. This SONOS flash arrays with the common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cells is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$ . To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and bit line method are selected as the program and 4he erase operation, respectively. The disturbance characteristics ,according to the program/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• ETRI Journal
• /
• 제44권3호
• /
• pp.504-511
• /
• 2022

Monte Carlo simulations show that, as temperature increases, the average kinetic energy of channel electrons in a GaN transistor first decreases and then increases. According to the calculations, the relative energy change reaches 40%. This change leads to a reduced barrier height due to quantum coupling among the three-dimensional motions of channel electrons. Thus, an analysis and physical model of the gate leakage current that includes drift velocity is proposed. Numerical calculations show that the negative and positive temperature dependence of gate leakage currents decreases across the barrier as the field increases. They also demonstrate that source-drain voltage can have an effect of 1 to 2 orders of magnitude on the gate leakage current. The proposed model agrees well with the experimental results.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
• /
• pp.120-120
• /
• 2006

탄소나노튜브는 nm급의 크기에 높은 전기전도도, 열전도 효율, 감한 기계적 강도 등의 장점을 가지며, FED(Field Emission Display), 극미세 전자 스위칭 소자, SET(Single Electron Transistor), AFM(Atomic Force Microscope) tip등 여러 분야로의 응용을 연구하고 있다. 본 연구에서는 탄소나노튜브를 Si 웨이퍼 위에 Ni/Ti 금속층을 촉매층으로 사용하고, 암모니아($NH_3$)가스와 아세틸렌 ($C_2H_2$)가스를 각각 희석가스와 성장원으로 사용하여 합성하였다. 탄소나노튜브의 성장은 Hot filament 화학기상증측(HFPECVD) 방식을 사용하였으며, 이 방법은 다량의 합성, 높은 균일성, 좋은 정렬 특성등의 장점을 가진다. 성장 온도는 탄소나노튜브의 성장 특성을 변화시키는 중요한 요소이다. 성장 온도에 따라 수직적 성장, 성장 밀도등의 특성 변화를 관찰하였다. 성장된 탄소나노튜브층 성분 분석은 에너지 분산형 X-선 측정기(EDS)를 통해 관찰하였고, 끝단에 촉매층이 존재하는 30~50 nm 폭을 가진 다중벽 탄소나노튜브를 고배율 투과전자현미경(HRTEM) 분석을 통해 관찰하였다. 전계방사 주사전자현미경(FESEM) 분석을 동해 1~3${\mu}m$의 길이를 가진 탄소나노튜브가 높은 밀도로 성장된 것을 확인하였다.

• 한국산학기술학회논문지
• /
• 제10권12호
• /
• pp.3626-3631
• /
• 2009

본 논문에서는 아날로그 회로에 사용되는 NMOSFET에 대한 Hot-Carrier 열화특성을 조사하였다. 여러 값을 갖는 게이트 전압으로 스트레스를 인가한 후, 소자의 파라미터 열화를 포화 영역에서 측정하였다. 스트레스 게이트 전압의 범위에 따라 계면 상태(interface state) 뿐 아니라 전자와 정공의 포획이 드레인 근처 게이트 산화막에서 확인되었다. 그리고 특히 낮은 게이트 전압의 포화영역에서는 정공의 포획이 많이 발생하였다. 이러한 전하들의 포획은 전달 컨덕턴스 ($g_m$) 및 출력 컨덕턴스 ($g_{ds}$)의 열화의 원인이 된다. 아날로그 동작 범위의 소자에서 파라미터 열화는 소자의 채널 길이에 매우 민감하게 반응한다. 채널길이가 짧을수록 정공 포획이 채널 전도도에 미치는 영향이 증가하게 되어 열화가 증가되었다. 이와 같이 아날로그 동작 조건 및 아날로그 소자의 구조에 따라 $g_m$ 및 $g_{ds}$의 변화가 발생하므로 원하는 전압 이득($A_V=g_m/g_{ds}$)을 얻기 위해서는 회로 설계시 이러한 요소들에 대한 고려가 필요하다.

• 한국전기전자재료학회논문지
• /
• 제24권6호
• /
• pp.433-439
• /
• 2011

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.