• 한국분말재료학회지
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• 제18권6호
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• pp.482-487
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• 2011

Alloy 617, Ni-22Cr-12Co-9Mo base oxide dispersion strengthened alloy was fabricated by using mechanical alloying, hot isostatic pressing and hot rolling. Uniaxial tensile tests were performed at room temperature and at $700^{\circ}C$. Compared with the conventional Alloy 617, ODS alloy showed much higher yield strength and tensile strength, but lower elongation. Fracture surfaces of the tensile tested specimens were investigated in order to find out the mechanism of fracture mode at each test temperature. Grain adjustment during tensile deformation was analyzed by electron backscattered diffraction mapping, inverse pole figures and TEM observation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• 한국진공학회지
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• 제16권3호
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• pp.187-191
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• 2007

본 연구에서는 실리콘 웨이퍼 위에 마그네트론 스퍼터링 시스템을 이용하여 Ni 촉매 층을 증착시키고, $NH_3$와 $C_2H_2$ gas를 이용하여 탄소나노튜브를 성장시켰다. Hot-filament 플라즈마 화학기상 증착법으로 탄소나노튜브의 성장 온도는 350, 450, 550, $650^{\circ}C$로 변화시켰으며, 성장되어진 탄소나노튜브는 field emission scanning electron microscope(FESEM) 분석을 하여 관찰하였고, 접촉각 측정법을 이용하여 탄소나노튜브 층의 특성을 분석하였다. 결과적으로 성장 온도는 탄소나노튜브의 성장 특성을 변화시키는 중요한 요소이다.

• 한국정보전자통신기술학회논문지
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• 제11권2호
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• pp.189-194
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• 2018

현재 대부분의 집적회로는 bulk CMOS 기술을 사용해서 제작되고 있으나 전력 소모를 낮추고 die 크기를 줄이기에는 한계점에 도달해있다. 이러한 어려움을 획기적으로 극복할 수 있는 초저전력 기술로서 SOI CMOS 기술이 최근에 크게 각광을 받고 있다. 본 논문에서는 100 nm Thin SOI 기판 위에 제작된 n-채널 MOSFET 소자들의 열전자 효과들의 온도 의존성에 관한 연구 결과들이 논의되었다. 소자들이 LDD 구조를 갖고 있음에도 불구하고 열전자 효과들이 예상보다 더 심각한 것으로 나타났는데, 이는 채널과 기판 접지 사이의 직렬 저항이 크기 때문인 것으로 믿어졌다. 온도가 높을수록 채널에서의 phonon scattering의 증가와 함께 열전자 효과는 감소하였는데, 이는 phonon scattering의 증가는 결과적으로 열전자의 생성을 감소시켰기 때문인 것으로 판단된다.

• 열처리공학회지
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• 제14권2호
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• pp.96-102
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• 2001

$Al_2O_3$-copper alloy has been successfully made by gas atomization, mechanical alloying and hot pressing. In order to investigate microstructure and phase, it has been studied by using scanning electron microscope, transmission electron microscope and X-ray diffractometor. Mechanical properties have been examined using hardness tester and compressive tester according to annealing temperature. Although comparatively large Cu-Al powders are milled, the reaction between Cu-Al and $Cu_2O$ occurs and very fine $Al_2O_3$ particles in the matrix particles (5-10nm) are obtained. Compressive strength of this alloy is more than that of GlidCop Al60.

• 한국레이저가공학회지
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• 제4권1호
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• pp.39-48
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• 2001

This study was performed to evaluate basic characteristics of electron beam weldability for high strength aluminum alloys. The aluminum alloys used were A5083 and A6N01, and A7N01. The principal welding process parameters, such as accelerating voltage, beam current, welding speed and chamber pressure were investigated. The dimension and microstructure of welds were evaluated with OLM, and SEM (EDAX). In addition, weldability variation(cracking) due to process parameters was also evaluated. The degree of cracking in the EB fusion zone appears to be affected mainly by aspect ratio, such that as aspect ratio increases the cracking tendency also increases. The alloying element itself may also affect the hot cracking resistance, but its role is considered to be indirect effect such that the relatively higher vaporization pressure elements of Zn and Mg give deeper weld penetration and thus results in greater cracking tendency.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 추계학술대회 논문집 학회본부
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• pp.363-367
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• 1988

A simple analytical model for the lateral channel electric field in gate - offset structured Lightly Doped Drain MOSFET has been developed. The model's results agree well with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field as function of drain and gate bias conditions and process, design parameters. Advantages of analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate / drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot - electron phenomena, individually. We are able to find the optimum doping concentration of LDD minimizing the peak electric field and hot - electron effects.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.258-258
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• 2010

In this work, back bias effects in the program of the silicon-oxide-nitride-oxide-silicon (SONOS) cell using two-step pulse sequence, are investigated. Two-step pulse sequence is composed of the forward biases for collecting the electrons at the substrate terminal and back bias for injecting the hot electrons into the nitride layer. With an aid of the back bias for electron injection, we obtain a program time as short as 600 ns and an ultra low-voltage operation with a substrate voltage of -3 V.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• 대한전자공학회논문지
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• 제14권3호
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• pp.6-11
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• 1977

GaAs Schottky Barrier Gate 전계효과트랜지스터의 잡음동작을 잡음등가회로를 사용하여 연구하였으며, 부가구인 잡음근원은 pinch-off영역에서 GaAs FET bias에 의하여 구현되었다. 이것이 바로 intervalley 산란잡음과 hot electron에 의한 잡음이었다. 본 논문의 잡음등가회로에서는 carrier의 포화속도와 기생저항의 영향을 고려한 parameter를 정하였다.