• 한국진공학회지
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• 제13권1호
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• pp.22-28
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• 2004

본 논문은 탄탈 박막의 증착시 음의 기판 바이어스에 의한 탄탈 박막내의 불순물 농도변화에 대해서 고찰하였다. 탄탈 박막은 실리콘 기판 위에 이온빔 증착장비를 이용하여 기판 바이어스를 걸지 않은 경우와 -125 V의 기판 바이어스를 건 상태에서 증착하였다. 탄탈 박막내의 불순물 농도를 관찰하기 위해서 이차이온 질량분석기(secondary ion mass spectrometry)를 이용하였다. 세슘 클러스터 이온에 의한 깊이분석에서, -125 V의 기판 바이어스를 걸어줌으로써 산소, 탄소, 그리고 실리콘 불순물의 농도가 기판 바이어스를 걸지 않은 경우에 비해 상당히 감소한 것을 알 수 있었다. 또한, 세슘 이온빔과 산소 이온빔을 이용한 전체 불순물의 농도분포에서도, 음의 기판 바이어스가 박막 증착시 각각의 불순물 농도에 영향을 준다는 결과를 얻었고 이에 대한 고찰을 하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.703-706
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• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

• 한국표면공학회지
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• 제39권3호
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• pp.87-92
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• 2006

The characteristic of interface layer and the effect of bias voltage on the microstructure of c-BN films were studied in the microwave plasma hot filament C.V.D process. c-BN films were deposited on a high speed steel(SKH-51) substrate by hot filament CVD technique assisted with a microwave plasma to develop a high performance of resistance coating tool. c-BN films were obtained at a gas pressure of 20 Torr, vias voltage of 300 V and substrate temperature of $800^{\circ}C$ in $B_2H_6-NH_3-H_2$ gas system. It was found that a thin layer of hexagonal boron nitride(h-BN) phase exists at the interface between c-BN layer and substrate.

• 전기학회논문지
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• 제61권1호
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• pp.89-93
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• 2012

c-BN films were deposited on SKH-51 steels by electron assisted hot filament CVD method and microstructure development was studied processing parameters such as bias voltage, temperature, etching and phase transformation at boundary layer between BN compound and steel to develop a high performance wear resistance tools. A negative bias voltage higher than 200V at substrate temperature of $800^{\circ}C$ and gas pressure of 20 torr in B2H6-NH3-H2 gas system was one of optimum conditions to produce c-BN films on the SKH-51 steels. Thin layer of hexagonal boron nitride phase was observed at the interface between c-BN layer and substrate.

• 한국표면공학회지
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• 제31권6호
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• pp.317-324
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• 1998

TiN and TiCN films were deposited on the high speed steel by Cathode Arc Ion Plating(CAIP) Process to investigate the tool life extension effect. The experiment variables were bias voltage and deposit time for the TiN coating and reactive gas flow rate ($CH_4:N_2$) under fixing deposit pressure, are current, bias voltage for the TiCN coating respectively. The micro structure and mechanical properties were investigated and compared for among the coating conditions using various methods and machining practice.

• 전기학회논문지
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• 제56권8호
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• pp.1445-1449
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• 2007

This paper presents the DOD (Drop-On-Demand) characteristic using the electrostatic field induced inkjet printing system. In order to achieve the DOD characteristic of electrostatic field induced inkjet printing, applied the bias voltage of 1.4 kV and the pulse voltage of $2.0\;kV\;{\sim}\;2.7\;kV$ using high voltage pulse generator. Electrostatic field induced droplet ejection is directly observed using a high-speed camera and for investigated DOD characteristic, CNT ink used. The electrostatic field induced inkjet head system has DOD characteristic using pulse generator which can be applied pulse voltage. The bias voltage has a good condition which form meniscus and has micro dripping mode for small size micro droplet. Also, the droplet size decreases with increasing the applied pulse voltage. This paper shows DOD characteristic at electrostatic field induced inkjet head system, Therefore. electrostatic DOD inkjet head system will be applied industrial area comparing conventional electrostatic inkjet head system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.472-474
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• 1995

A Sputter ion Plating(SIP) system with a r.f. coil electrode and the Facing Target Sputter(FTS) source was designed for high-quality thin film formation. The rf discharge was combined with DC facing target sputtering in order to enhance ionization degree of a sputtered atoms. The energy of ions incident on the substrate depended on the health potential of DC biased substrate. The mean impact ion energy increased with negative bias voltage and rf power. The adhesive force of the TiN film formed was in the range of 30$\sim$50N, and markedly influenced by substrate bias voltage.

• 전력전자학회논문지
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• 제8권1호
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• pp.24-29
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• 2003

현재 120kV/70A 고압 스위치가 KSTAR의 NBI 시스템에 사용되기 위하여 대전의 원자력 연구소에 설치되어 있다. NBI 시스템은 아크 발생시 이온 소스를 보호하기 위하여 전압의 빠른 차단 및 빔 전류의 유시를 위하여 전압의 빠른 턴온이 요구된다. 따라서 고압 스위치와 아크 검출회로는 NBI 시스템에서 중요한 부분을 차지하고 있다. 고압의 반도체 스위치는 NBI 시스템 뿐만 아니라 산업전반에서 요구되고 있다. NBI 시스템에 적용된 120kV/70A 고압 스위치는 100개의 MOSFET 소자를 직렬연결하였으며 본 논문에서 제안한 바이어스 전원이 없는 간단한 구동회고를 사용하였다. 실험식에서의 시험 및 현장에서 100kW의 모의 저항부하와 NBI 이온 소스에 적용한 실험결과를 제시하였다. 본 논문은 120kV/70A 고압 MOSFET 스위치와 간단한 게이트 구동회로의 설계를 제시하였으며, 제작 및 시험기간 동안의 문제점 및 해결방안에 대해서도 제시하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1185-1188
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• 2007

The address discharge characteristics by the various scan-low and common-bias voltages are investigated based on measured address discharge time lags and $V_t$ close-curve analysis. The scan-low voltages are changed under the same voltage difference between the X and Y electrodes during an address period. As the voltage difference between the scan and address electrodes is increased during an address period, the address discharge time lag is shortened but the background luminance is increased. It is found that the improved address discharge characteristics is caused by the effect of the higher external applied voltage during an address period than the accumulated wall charges during a reset period and the high background luminance can be prevented by applying an address-bias voltage during a rising-ramp period and low reset voltage.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.517-520
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• 2002

This paper has been studied Operational Amplification Circuit that has high power specification of 90 W is designed. In the input differential amplifier stage, the current source for circuit bias is designed to protect device from high voltage source. the criving state has the voltage gain more than input differential stage. With temperature compensation design, output stage works stable in different to temperature.