• Title/Summary/Keyword: High-voltage bias

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Suppression of silicon clusters using a grid mesh under DC bias

  • Kim, Yonwon;Kang, Jun
    • Journal of Advanced Marine Engineering and Technology
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    • v.41 no.2
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    • pp.146-149
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    • 2017
  • Si clusters generated during the plasma chemical vapor deposition (CVD) process have a great influence on the quality of the fabricated films. In particular, in hydrogenated amorphous silicon thin films (a-Si:H) used for thin film solar cells, Si clusters are mainly responsible for light-induced degradation. In this study, we investigated the amount of clusters incorporated into thin films using a quartz crystal microbalance (QCM) and specially designed cluster eliminating filters, and investigated the effect of the DC grid mesh in preventing cluster incorporation. Experimental results showed that as the applied voltage of the grid mesh, which is placed between the electrode and the QCM, decreased, the number of clusters incorporated into the film decreased. This is due to the electrostatic force from the grid mesh bias, and this method is expected to contribute to the fabrication of high-quality thin films by preventing Si cluster incorporation.

Fabrication and Characterization of Power AlGaAs/InGaAs double channel P-HEMTs for PCS applications (PCS용 전력 AlGaAs/InGaAs 이중 채널 P-HEMTs의 제작과 특성)

  • 이진혁;김우석;정윤하
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.295-298
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    • 1999
  • AlGaAs/InGaAs power P-HEMTS (Pseudo-morphic High Electron Mobility Transistors) with 1.0-${\mu}{\textrm}{m}$ gate length for PCS applications have been fabricated. We adopted single heterojunction P-HEMT structure with two Si-delta doped layer to obtain higher current density. It exhibits a maximum current density of 512㎃/mm, an extrinsic transconductance of 259mS/mm, and a gate to drain breakdown voltage of 12.0V, respectively. The device exhibits a power density of 657㎽/mm, a maximum power added efficiency of 42.1%, a linear power gain of 9.85㏈ respectively at a drain bias of 6.0V, gate bias of 0.6V and an operation frequency of 1.765㎓.

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The design of large-signal power amplifier using waveform analysis (파형 분석을 통한 대신호 전력증폭기의 설계)

  • 이승준;김병성;남상욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.4
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    • pp.1121-1133
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    • 1998
  • In this paper, a new method is proposed for a simple andaccurate design of larage-sigal power amplifier using the output current- and volage- waveform analysis. An existing high-efficiency theory, Harmonic Loading, is modified to apply to a real device, and the notion of "actual bias point at large-signal input" is proposed. Based on the proposed theory, 2GHz band poweramplifier is implemented using HEMT device, and the implemented amplifier shows 14dBm output power, 46% drain efficienty, 38% power-added efficiency and 7.8dB gain at 2V bias voltage.

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Negative Dynamic Resistance and RF Amplification in Magnetic Tunnel Junctions

  • Tomita, Hiroyuki;Maehara, Hiroki;Nozaki, Takayuki;Suzuki, Yoshishige
    • Journal of Magnetics
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    • v.16 no.2
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    • pp.140-144
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    • 2011
  • We report on a numerical calculation study of two new functional properties in magnetic tunnel junctions (MTJs), negative dynamic resistance and RF amplification. The magnetic dynamics in a conventional CoFeB/MgO/CoFeB MTJ with in-plane magnetization was investigated using a macro-spin model simulation. To examine the influence of thermal fluctuations, random external magnetic fields were also included. Using a voltage controlled bias circuit, the negative dynamic resistance was obtained from time averaged I-V characteristics at both 0 K and 300 K under appropriate external magnetic fields and bias voltages. Using this negative dynamic resistance property, we demonstrated RF amplification with a 100 MHz high frequency signal. Sizable RF amplification gain was observed without thermal fluctuation. However, at 300 K, the RF signal was not amplified because low frequency magnetization dynamics were dominant.

ANALYSIS OF THE MUTUAL SELF-BIASED SHIELDED MAGNETO-RESISTIVE HEAD WITH TRANSMISSION-LINE MODEL(II)

  • Zhang, H.W.;Kim, H.J.
    • Journal of the Korean Magnetics Society
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    • v.5 no.4
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    • pp.299-303
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    • 1995
  • In order to improve the read-out signal waveform, a shielded magnetoresistive (SMR) head has been designed and studied by applying the transmission-line model. The bias and signal field distribution, the voltage output, the harmonic output signal and resistance value of MR element are simulated as functions of bias current and recording displacement. The results show that the SMR head has good linear character with respect to the medium recording signal in high recording frequency of about 2.5 MHz. The amplitude and waveform of reroduction signal have been obviously improved. The saturation effect on the symmetry and amplitude of reproducing output have also been analyzed.

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AC dielectric response of poly(p-phenylenevinylene) light emitting devices (주파수 의존성에 따른 고분자 LED의 유전 분산 거동에 관한 연구)

  • 이철의;김세헌;장재원;김상우
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.11a
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    • pp.149-152
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    • 2000
  • AC impedance measurements on poly-p-phenylenevinylene (PPV) LEDs in the frequency range between 10 Hz and 10$\^$6/ Hz were carried out. The complex-plane impedance spectra indicate that PPV devices can be represented by equivalent circuits that corresponds to the bulk and interfacial regions at high and low frequencies, respectively. As a result of complex impedance analysis through the separation of bulk and interfacial region impedances, increase of forward bias in Al/PPV/ITO devices gave rise to relative decrease of the interfacial region impedance. Above the electric field of 10$\^$6/ V/cm the PPV device showed a space charge limited current (SCLC) conduction. The dependence of the transport mechanism and dielectric properties on the applied bias voltage is discussed.

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Hydrocarbon Plasma of a Low-Pressure Arc Discharge for Deposition of Highly-Adhesive Hydrogenated DLC Films

  • Chun, Hui-Gon;Oskomov, Konstantin V.;Sochugov, Nikolay S.;Lee, Jing-Hyuk;You, Yong-Zoo;Cho, Tong-Yul
    • Journal of the Semiconductor & Display Technology
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    • v.2 no.1
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    • pp.1-5
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    • 2003
  • Plasma generator based on non-self-sustained low-pressure arc discharge has been examined as a tool for deposition of highly-adhesive hydrogenated amorphous diamond-like carbon(DLC) films. Since the discharge is stable in wide range of gas pressures and currents, this plasma source makes possible to realize both plasma-immersion ion implantation(PIII) and plasma-immersion ion deposition(PIID) in a unified vacuum cycle. The plasma parameters were measured as functions of discharge current. Discharge and substrate bias voltage parameters have been determined for the PIII and PIID modes. For PIID it has been demonstrated that hard and well-adherent DLC coating are produced at 200-500 eV energies per deposited carbon atom. The growth rates of DLC films in this case are about 200-300 nm/h. It was also shown that short(∼60$\mu\textrm{s}$) high-voltage(> 1kV) substrate bias pulses are the most favorable for achieving high hardness and good adhesion of DLC, as well as for reducing of residual intrinsic stress are.

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Solution-Processed Indium-Gallium Oxide Thin-Film Transistors for Power Electronic Applications (전력반도체 응용을 위한 용액 공정 인듐-갈륨 산화물 반도체 박막 트랜지스터의 성능과 안정성 향상 연구)

  • Se-Hyun Kim;Jeong Min Lee;Daniel Kofi Azati;Min-Kyu Kim;Yujin Jung;Kang-Jun Baeg
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.37 no.4
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    • pp.400-406
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    • 2024
  • Next-generation wide-bandgap semiconductors such as SiC, GaN, and Ga2O3 are being considered as potential replacements for current silicon-based power devices due to their high mobility, larger size, and production of high-quality wafers at a moderate cost. In this study, we investigate the gradual modulation of chemical composition in multi-stacked metal oxide semiconductor thin films to enhance the performance and bias stability of thin-film transistors (TFTs). It demonstrates that adjusting the Ga ratio in the indium gallium oxide (IGO) semiconductor allows for precise control over the threshold voltage and enhances device stability. Moreover, employing multiple deposition techniques addresses the inherent limitations of solution-processed amorphous oxide semiconductor TFTs by mitigating porosity induced by solvent evaporation. It is anticipated that solution-processed indium gallium oxide (IGO) semiconductors, with a Ga ratio exceeding 50%, can be utilized in the production of oxide semiconductors with wide band gaps. These materials hold promise for power electronic applications necessitating high voltage and current capabilities.

The control of the structure and properties of tetrahedral amorphous carbon films prepared by Filtered Vacuum Arc (FVA 증착법에 의해 합성된 ta-C 박막의 구조 및 물성 제어)

  • 이철승;신진국;김종국;이광렬;윤기현
    • Journal of the Korean Vacuum Society
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    • v.11 no.1
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    • pp.8-15
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    • 2002
  • Tetrahedral amorphous carbon(ta-C) films were deposited by the filtered vacuum arc(FVA) process. The FVA process has many advantages such as high ionization ratio and the ion energy, which is suitable for dense amorphous carbon film deposition. However, the energy of the carbon ion cannot be readily controlled by manipulating the arc source parameters. In order to control the film properties in wide range, we investigated the dependence of the film properties on the substrate bias voltage. The mechanical properties and the density of the film exhibit the maximum values at about -100 V of the bias voltage. The maximum values of hardness and density were respectively 54$\pm$3 GPa and 3.6$\pm$0.4 g/㎤, which are 3 to 5 times higher than those of the films deposited by RF PACVD or ion beam process. The details of the atomic bond structure were analysed by Raman and NEXAFS spectroscopy. The change in the film properties for various bias voltages could be understood in the view of the $sp^2$ and $sp^3$ bond fraction in the deposited films.

Design of an EEPROM for a MCU with the Wide Voltage Range

  • Kim, Du-Hwi;Jang, Ji-Hye;Jin, Liyan;Ha, Pan-Bong;Kim, Young-Hee
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.4
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    • pp.316-324
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    • 2010
  • In this paper, we design a 256 kbits EEPROM for a MCU (Microcontroller unit) with the wide voltage range of 1.8 V to 5.5 V. The memory space of the EEPROM is separated into a program and data region. An option memory region is added for storing user IDs, serial numbers and so forth. By making HPWs (High-voltage P-wells) of EEPROM cell arrays with the same bias voltages in accordance with the operation modes shared in a double word unit, we can reduce the HPW-to-HPW space by a half and hence the area of the EEPROM cell arrays by 9.1 percent. Also, we propose a page buffer circuit reducing a test time, and a write-verify-read mode securing a reliability of the EEPROM. Furthermore, we propose a DC-DC converter that can be applied to a MCU with the wide voltage range. Finally, we come up with a method of obtaining the oscillation period of a charge pump. The layout size of the designed 256 kbits EEPROM IP with MagnaChip's 0.18 ${\mu}m$ EEPROM process is $1581.55{\mu}m{\times}792.00{\mu}m$.