• Journal of the Korean Society of Fisheries and Ocean Technology
• /
• v.24 no.4
• /
• pp.172-179
• /
• 1988

A cartridge type hydraulic logic valve consists of simple two port valve whose poppet is closed or opened by means of pressure signal of a pilot line. Accordingly, the logic valve can be used not only for direction, flow and pressure control purpose but also for versatile function valve which enables all above mentioned functions. In addition, the valve has little internal leakage and pressure loss, superior response characteristics and easiness in making small block type valve. The above mentioned good performances being recognized recently, the logic valve has been used widely in the large scale hydraulic system such as a hydraulic press system, for the performance requirements of high speed operation and precise control characteristics. However, there are scarce reports until now, except for a few ones from Aachen Institute of Technology in West Germany, so it is necessary to be studied on development and investigation for practical application. This paper showed that the static and dynamic characteristics of a logic valve when the logic valve is used for directional control, to investigate the relations between the valve operating characteristics and the valve design conditions. From the above mentioned procedure, it was ascertained that the valve operation characteristics obtained by numerical analysis showed good agreements with experimental results. The representative results obtained are as follows; 1. During the valve is closing, the poppet velocity is almost constant in the logic valve. 2. The pilot pressure P sub(3) and the resistance R in the pilot line have much influences on the valve operation time. 3. Spring strength have not such a severe influence on the valve operating time. 4. The operation characteristics of the logic valve can be estimated with good accuracy comparatively by numerical analysis with the equations describing poppet motion.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.16 no.2
• /
• pp.45-53
• /
• 2002

This paper presents an algorithm for the appropriate parameter selection of a power system stabilizer and power converters in two-area power systems with a series HVDC links. The method for PSS is one of the classical techniques by allocating properly poly-zero positions to fit as closely as desired the ideal phase lead and by changing the gain to produce a necessary damping torque. Proper parameter of power converters are obtained in order to have sufficient speed and stability margin to cope with changing reference values and disturbances based on the Root-locus technique. The small signal and transient stability studies using the PSS and power converters parameters obtained from these methods show that a natural oscillation frequency of the study case system is adequately damped. The simulation used in the paper was performed by the Power System Toolbox software program based on MATLAB.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.37A no.10
• /
• pp.827-833
• /
• 2012

The receiver performance is degraded by nonlinear memory problem in communication system. The pre-distorter techniques are an effective technique to compensate for the nonlinear distortion of the HPA without memory effects. However, memory effect of HPA can no longer be ignored when data signal is transmitted in high speed. Many adaptive pre-distorter schemes have been studied to compensate for memory effect problem of HPA in transmitter. The complexity and cost of satellite will increase when using adaptive pre-distorter in satellite communication system. In this paper, we propose receiver feedback closed loop pre-distortion technique in order to compensate for nonlinear problem of HPA with memory problem. The purpose of this paper is to reduce complexity and cost of satellite design by using only pre-distorter at terrestrial station.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.22 no.5
• /
• pp.29-38
• /
• 1985

In this paper we have designed and implemented in real time a simple, efficient and flexible AOPCM cosec using a high speed digital processor, NEC 7720. For ADPCM system, we have used an instantaneous adaptive quantizer and a first-order fixed predictor. The software for NEC 7720 has been developed and it was found that the NEC 7720 was capable of performing the entire ADPCAt algorithm for 4 channels in real time as optimizing the program. Computer simulation has born made to investigate a computational accuracr of NEC 7720 and to de-termine necessary parameters for a ADPCM codec. Real telephone speech, RC-shaped Gaussian noise and 1004 Hz tone signal were used for simulation. In simulation, the parameters werc optimized from the computed SNR and the informal listening test. The developed software was tested in real time operation using a hardware emulator for NEC 7720. It took a maximum 23.25$\mu$s to encode one sample and 113.5$\mu$s, including all the necessary 1/0 operations, to encode 4 channels. In the case of decoding process, it took 24.75$\mu$s to decode one sample and 119.5$\mu$s to decode 4 channels.

• Korean Journal of Optics and Photonics
• /
• v.19 no.1
• /
• pp.36-42
• /
• 2008

Implementation of a wavelength-swept source with constant tuning rate adopting a PZT-type tunable filter, requires the knowledge of hysteresis of the filter used. The hysteresis must be considered to avoid any degradation in resolution of the optical frequency domain reflectometry (OFDR) system. An optical spectrum analyzer (OSA) could be used to do the hysteresis measurement, but its measurement time is too long for the high-speed driving conditions for the filter. We proposed a new hysteresis measurement method based on OFDR, which could measure the hysteresis in a real driving condition. A hysteresis measurement apparatus consisted of wavelength-swept source, interferometer, signal processing unit, and PC program is built and used to do the measurement. It is concluded that the new method is useful in the measurement of hysteresis at real driving conditions by successfully implementing a swept-wavelength source whose wavelength change is linear in time.

• Korean Journal of Optics and Photonics
• /
• v.16 no.6
• /
• pp.527-534
• /
• 2005

We investigate the pulsation characteristics in a multi-section DFB laser which is composed of one DFB section, phase tuning section, and gain section. Multi-section DFB lasers with anti-phase (AP) complex-coupled (CC) DFB structure show wide current ranges of gain and phase tuning sections fer stable pulsations compared to those with in-phase CC DFB structure or index-coupled DFB structure. For multi-section DFB lasers with AP CC DFB structure, the current range of a gain section for stable pulsations increases and the tuning range of the pulsation frequency increases as a coupling strength or a gain coupling coefficient increases Also, the tuning range using the phase variation in a phase tuning section increases. For a fixed coupling strength, the current ranges of gain and phase tuning sections for stable pulsations increase and the tuning range of the pulsation frequency increases as the length of a DFB section increases.

• Journal of the Korea Society of Computer and Information
• /
• v.8 no.2
• /
• pp.97-105
• /
• 2003

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The Proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output Port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms . The proposed switch acquires control over priority transmission through the REd signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the proposed switch under non-uniform random traffic conditions.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.36S no.9
• /
• pp.1-8
• /
• 1999

In this paper, we propose and analyze a concatenated coding scheme for DS/CDMA systems in asynchronous channels. In the concatenated coding, bandwidth efficient $2^{2L-2}$-state ${\frac{L}{L+1}}$-rate 2-MTCM with biorthogonal signal constellation is used for the inner code, and $(2^{L-1},\;{\lceil}\frac{2^{L-1}}{L/2}{\rceil})$ RS code is use for the outer code. It is shown that we can get considerable performance gain over the uncoded system without sacrificing the data transmission rate. The proposed system can be used as a coding scheme for reliable and high speed integrated information services of mobile communication systems.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.7
• /
• pp.30-38
• /
• 2012

This paper presents packet detection, frequency offset estimation architecture and performance analysis for OFDM-based wireless personal area network (WPAN) systems. Packet detection structure is used to find the start point of a packet exactly in WPAN system as the correlation value passes the constant threshold value. The applied autocorrelation structure of the algorithm can be implemented simply compared to conventional packet detection algorithms. The proposed frequency offset estimation architecture is designed for phase rotation process structure, internal bit reduction to reduce hardware size and the frequency offset adjustment block to reduce look-up table size unlike the conventional structure. If the received signal can be compensated by estimated frequency offset through the correction block, it can reduce the impact on the frequency offset. Through the performance result, the proposed structure has lower hardware complexity and gate count compared to the conventional structure. Thus, the proposed structure for OFDM-based WPAN systems can be applied to the initial synchronization process and high-speed low-power WPAN chips.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.7
• /
• pp.1442-1447
• /
• 2004

In this paper, a 6-Bit CMOS Folding and Interpolating AD Converter is presented. The converter is considered to be useful as an integrated part of a VLSI circuit handling both analog and digital signals as in the case of HDD or LAN applications. A built-in analog circuit for VLSI of a high-speed data communication requires a small chip area, low power consumption, and fast data processing. The proposed folding and interpolating AD Converter uses a very small number of comparators and interpolation resistors, which is achieved by cascading a couple of folders working in different principles. This reduced number of parts is a big advantage for a built-in AD converter design. The design is based on 0.25m double-poly 2 metal n-well CMOS process. In the simulation, with the applied 2.5V and a sampling frequency of 500MHz, the measurements are as follows: power consumption of 27mw, INL and DNL of $\pm$0.1LSB, $\pm$0.15LSB each, SNDR of 42dB with an input signal of 10MHz.