• The Transactions of the Korea Information Processing Society
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• v.7 no.5
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• pp.1553-1558
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• 2000

The development of recent computer and communication technology has changed Automation System using communication network, and the new USB substituted with Serial Communication is already developed and now popular. In this paper, High speed data transfer system design using USB interface and communication application simulated for the situation is introduced. Base on USB, we can use additive function efficiently coped with former field device. The 'Winsock Connection USB Ternimal,' designed for hardware simulation, control the field device connected by USB, and provide the way for remote control of field device by Telnet connection through TCP/IP. That theorem can guarantee controlling direct input dta of user, and acuate function of field device using USB Packet Transmission. As a result of amy research, this communication application system identified good operation of field device with those of former field device. Another result of the experiment of hardware operation, we obtained accomplishment that the sufficient bandwidth guarantee of USB has high speed and high performance, and reduce the occupancy of system.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.46-55
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• 2014

PCB design technology for high-speed transmission line has been developed continuously. Adapting to the high capacity of the communication system, switch fabric interface used for backplane is being standardized to accommodate more than 10Gbps serial interface. In this paper, various computer simulations are performed to compare the performance of each transmission line per length according to PCB material, and also to analyze the effect from via stub length and crosstalk, for the purpose of applying 11.5Gbps serial interface as a switch fabric interface in tera-bit switching system. As a result of the simulation, important design issues, such as PCB material of each board supporting 8dB improvement in transmission loss using low loss PCB, maximum available stub length on transmission line via, whether or not to apply the backdrill process to the via, and the clearance of the differential pair between transmission lines, are determined. The most efficient system architecture which could be applied 11.5Gbps serial interface in all switch fabric interfaces is defined from the simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.776-783
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• 2009

Current-cut circuit is an effective method to obtain low power consumption in wireless communication systems as high speed OFDM. For the operation of current-mode FFT LSI with analog signal processing essentially requires current-mode serial-to-parallel/parallel-to-serial converter with multi input and output structure. However, the Hold-mode operation of current-mode serial-to-parallel/parallel-to-serial converter has unnecessary power consumption. We propose a novel current-mode serial-to-parallel/parallel-to-serial converter with current-cut circuit and full chip simulation results agree with experimental data of low power consumption. The proposed current-mode serial-to-parallel/parallel-to-serial converter promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• Proceedings of the KWS Conference
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• 2001.05a
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• pp.49-51
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• 2001

• International Journal of Contents
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• v.9 no.1
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.141-149
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• 1999

If signal time duration of MC-CDMA method which has studied for next-generation high-speed data transmission is not sufficiently large compared to delay spread of channel, the performance is degraded by generation of intersymbol interference. In this paper, this problem will solve through serial to parallel convertor and make large sufficiently time duration of signal compared to delay spread of channel and rise variable spectral efficiency through the number of serial to parallel convertor subchannel we will add to parallel frequency diversity block for improve the performance in mobile Communication. Spectral efficiency of the proposed system is counted and compared to spectral efficiency of MC-CDMA and investigated through computer simulations by using multipath Rayleigh fading channel.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.519-523
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• 2003

This paper describes the communication system of sequencing sorter. Generally sequencing sorter is a machine that sorts mails by delivery order. And designed sequencing sorter is composed of 5 physical modules. So, it is necessary to communicate with each module and to control this communication. A computer called Machine Management Computer, controls this. This paper is about the communication system with MMC and module controllers. This is PC-based, asynchronous full-duplex 4-wire serial systems. 3 protocol layers are presented and stop-and-wait flow control is adopted. Because designed sequencing sorter has to be operated high speed about 27,000 letters per hour, we analyzed the network traffic in the worst case. So, we could find that the communication system has to use above 115,200bps speed.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1152-1156
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• 2003

For pneumatic valve system control, we need a serial data transmission system with high speed and reliability for information interchange between main computer and I/O devices. This paper presents a set of design techniques for a data communication system that is mainly used for pneumatic valve system control. For this purpose, we first designed hardware modules for an interface between central control module and local node that handles the operation of solenoid control valves. in addition, we developed a communication protocol for construction of rs-485 based multi-drop network and this protocol is basically designed with a kind of polling technique. Finally we evaluated performance of the developed system. the field test results show that, even under high noise environment, the data transmission of 375kbps rate is possible up to 1,500meter without using repeater. In addition, the system developed in this research is easily to be extended for a communication network because of its modular structure.

• Journal of Electrical Engineering and Technology
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• v.13 no.6
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• pp.2479-2484
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• 2018

The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.