• Proceedings of the Korean Information Science Society Conference
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• 2008.06a
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• pp.130-131
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• 2008

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2006.07a
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• pp.423-423
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• 2006

• 한국전산유체공학회:학술대회논문집
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• 2006.05a
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• pp.174-177
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• 2006

• Journal of the Korea Society of Computer and Information
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• v.14 no.11
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• pp.97-103
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• 2009

In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using $Nios^{(R)}$ II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-$70^{(R)}$ reference board. The designed Parallel processing system is master-slave, shared memory and MIMD(Mu1tiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.55-64
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• 1996

This paper presents performance evaluation of a new high speed inter-processor communication(HIPC) network for large capacity and high performance digitral switching system. The HIPC structure implements the fast reservation and concurrent arbitration technique (modified round-robin arbitration). The performance evaluation of HIPC was performed by not only computer simulation but also numerical approximation method which was derived for a single server multi-queue system with nonexhaustive cyclic service. The approximation results are almost same with that of computer simulation. The TDX-10 basic callscenario was applied to the HIPC netowrk and analyzed. these results were compared with TDX-10 IPC and shows that the difference of th emean waiting time in the TX buffer of NTP node increases sharply according to the increase of the message arrival rate.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.407-415
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• 2007

In parallel cluster computing systems, the efficiency of communication between computing nodes is one of important factors that decide overall system performance. Accordingly, many researchers have studied on high-performance inter-node communication. The recently launched multi-core processor, however. increases the importance of intra-node communication as well because the more the number of cores in a node, the more the number of parallel processes running in the same node. Though there have been studies on intra-node communications, these have limited considerations on the state-of-the-art systems. In this paper, we propose a Linux kernel module that minimizes the number of data copy by exploiting the memory mapping mechanism for high-performance intra-node communication. The proposed kernel module supports the Linux kernel version 2.6. The performance measurements over a multi-core system present that the proposed kernel module can achieve lower latency up to 62% and higher throughput up to 144% than an existing kernel module approach. In addition, the measurements reveal that the performance of intra-node communication can vary significantly based on whether the cores that run the communication processes are belong to the same processor package (i.e., sharing the L2 cache).

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1436-1439
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• 2002

In this paper, based on the data link model characterized by the spaceborne small SAR system, the high rate multi-channel data link module is designed including link storage, link processor, transmitter, and wide-angle antenna. The design results are presented with the performance analysis on the data link budget as well as the multi-mode data rate in association with the SAR imaging mode of operation from high resolution to the wide swath.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.921-924
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• 1993

For the purpose of applying to a high-speed control system, such as engine control for automobile application, we propose an architecture of a fuzzy inference processor, which can realize high-speed inference, high-resolution, and can be implemented with small chip area. We have designed a single chip based on the architecture, and confirmed the performance, such as 140 kFLIPS with 8-bit resolution.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.9
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• pp.873-880
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• 2008

This paper deals with the peer-to-peer data communication to connect each distributed levels of developed unmanned system according to the JAUS. The JAUS is to support the acquisition of unmanned system by providing a mechanism for reducing system life-cycle costs. Each of distributed levels of the JAUS protocol divides into a system, some of subsystems, nodes and components/instances, each of which may be independent or interdependence. We have to distribute each of the levels because high performance is supported in order to create several sub-processor computing data in one processor with high CPU speed performance. To complement such disadvantage, we must think the concept that a distributed processing agrees with separating each of levels from the JAUS protocol. Therefore, each of distributed independent levels send data to another level and then it has to be able to process the received data in other levels. So, peer-to-peer communication has to control a data flow of distributed levels. In this research, we explain each of levels of the JAUS and peer-to-peer communication structure among the levels using our developed unmanned ground vehicle.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.73-79
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• 2014

In this study, the unmanned vehicle to develop a preliminary step, we were facilities for Automated Guided Vehicle (AGV) simulator is designed and implemented. Industry is increasingly the more advanced automation and management systems need to be efficient. These studies are at least 24-hour continuous unmanned vehicles and personnel can result in reduction of labor costs. In addition, safety accidents can be minimized in the industry as an effect of intelligent AGV is essential. This study is the initial step for the development of AGV. manufactured simulator to Simulation and drives the performance of the system is evaluated. The configuration of the simulator, ultrasonic sensors, infrared sensors, and using the obstacle were to follow a given path. In addition, two-way communication between the host computer and the main processor that was. communication method that IEE802.11 meets the standard is applied to high-speed wireless LAN systems, each of the sensor information is calculated. AGV having a drive shaft 4 of the four wheels are respectively independent structure. AGV's main processor is driven using a high-performance DSP, and the controller controls the steering device of the load could be significantly reduced.