• Investigative Magnetic Resonance Imaging
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• v.10 no.2
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• pp.108-116
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• 2006

Purpose : High-resolution spiral-scan imaging is performed at 3 Tesla MRI system. Since the gradient waveforms for the spiral-scan imaging have lower slopes than those for the Echo Planar Imaging (EPI), they can be implemented with the gradient systems having lower slew rates. The spiral-scan imaging also involves less eddy currents due to the smooth gradient waveforms. The spiral-scan imaging method does not suffer from high specific absorption rate (SAR), which is one of the main obstacles in high field imaging for rf echo-based fast imaging methods such as fast spin echo techniques. Thus, the spiral-scan imaging has a great potential for the high-speed imaging in high magnetic fields. In this paper, we presented various high-resolution images obtained by the spiral-scan methods at 3T MRI system for various applications. Materials and Methods : High-resolution spiral-scan imaging technique is implemented at 3T whole body MRI system. An efficient and fast higher-order shimming technique is developed to reduce the inhomogeneity, and the single-shot and interleaved spiral-scan imaging methods are developed. Spin-echo and gradient-echo based spiral-scan imaging methods are implemented, and image contrast and signal-tonoise ratio are controlled by the echo time, repetition time, and the rf flip angles. Results : Spiral-scan images having various resolutions are obtained at 3T MRI system. Since the absolute magnitude of the inhomogeneity is increasing in higher magnetic fields, higher order shimming to reduce the inhomogeneity becomes more important. A fast shimming technique in which axial, sagittal, and coronal sectional inhomogeneity maps are obtained in one scan is developed, and the shimming method based on the analysis of spherical harmonics of the inhomogeneity map is applied. For phantom and invivo head imaging, image matrix size of about $100{\times}100$ is obtained by a single-shot spiral-scan imaging, and a matrix size of $256{\times}256$ is obtained by the interleaved spiral-scan imaging with the number of interleaves of from 6 to 12. Conclusion : High field imaging becomes increasingly important due to the improved signal-to-noise ratio, larger spectral separation, and the higher BOLD-based contrast. The increasing SAR is, however, a limiting factor in high field imaging. Since the spiral-scan imaging has a very low SAR, and lower hardware requirements for the implementation of the technique compared to EPI, it is suitable for a rapid imaging in high fields. In this paper, the spiral-scan imaging with various resolutions from $100{\times}100$ to $256{\times}256$ by controlling the number of interleaves are developed for the high-speed imaging in high magnetic fields.

• Journal of the Korean Professional Engineers Association
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• v.29 no.2
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• pp.15-23
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• 1996

With the ever-increasing importance of high-speed information in society as we move towards the 21 st century, telecommunication laboratories of advanced nations are pressing forward with research and development aimed at implementing its W & P(Visual Intelligent and Personal) services and construction of a new network to support them. In legals to the former, based on a long-term view of technological and market trends, those laboratories are researching and developing services that will make possible an effective progression from the development of services that answer to potential needs towards the full-scale implementation of VI & P services. In regards to the latter, these laboratories are responding in a flexible manner to the increasing diversity and disposal of the communications environment by separating the network into a transmission system and a versatile information control/conversion -ion system and laboratories are working at enhancing the performance of both. Within these board aims, the laboratories are currently focusing our attention in three areas : the technology for a high-speed broadband transmission system featuring optical frequency multiplexing and ATM techniques, network and software technologies for advanced information control and conversion, and technology for constructing a new access network that can provide a comprehensive range of multimedia services. This article describes the laboratories' concept of how VI & P services will develop in the future, and the latest trends in the field of communications. It also describes the ideal configuration of the new network and discusses the important technological aspects of how it is to be constructed. Finally, it presents the results of the laboratories'recent research which include some innovative work, point out the areas requiring future investigation.

• Journal of Korea Multimedia Society
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• v.14 no.7
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• pp.895-904
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• 2011

In welding machine that executes existing spot welding, wrong operation of system has often occurs because of their mechanical motion that can be caused by a number of supply like the welding object. In exposed working environment for various situations such as worker or related equipment moving into any place that we are unable to exactly distinguish between good and not condition of nut. Also, in case of defective welding of nut, it needs various evaluation and analysis through image processing because the problem that worker should be inspected every single manually. Therefore in this paper, if the object was not stabilization state correctly, we have purpose to algorithm implementation that it is to reduce the analysis time and exact recognition as to improve system of image processing. As this like, as image analysis for assessment whether it is good or not condition of nut, in his paper, implemented algorithms were suggested and list by group and that it showed the effectiveness through more than one experiment. As the result, recognition rate of normality and error according to the estimation time have been shown as 40%~94.6% and 60%~5.4% from classification 1 of group 1 to classification 11 of group 5, and that estimation time of minimum, maximum, and average have been shown as 1.7sec.~0.08sec., 3.6sec.~1.2sec., and 2.5sec.~0.1sec.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.61-74
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• 2005

Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.

• The KIPS Transactions:PartD
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• v.8D no.3
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• pp.285-294
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• 2001

Recently many efforts on the development of automatic processing system for delivery sequency sorting have been performed in ETRI, which requires the use of postal 4-state bar code system to encode delivery points. This paper addresses the issue on the extension of read range and the improvement of image processing method. For the improvement of image processing procedure, applied information acquisition method through basic two thresholds onto the horizontal axial line of gray image based on reference information of 4-state bar code symbology. Symbol values are computed after creating two threshold values based on the obtained information through search of horizontal axial values. The implementation result of 4-state bar code reader are obtained the symbol values within 30~60 msec (58,000~116,000 mail item/hour)without noise removal or image rotation in spite of the incline $\pm 45^{\circ}$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.637-637
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• 1997

In this paper, format conversion filters are proposed, which have advantages in hardware implementation compared to the ones proposed in MPEG-4 Video Verification Model. since each coefficients of the proposed filters is constrained to have less than two non-zero digits in minimal signed digit representation, multiplication of input and the coefficient can be implemented by a single adder. As a result, the proposed filters have advantages in hardware complexity and speed, compared to the filters which are usually implemented by integer multiplier or carry save adders. Six kinds of filters are proposed in MPEG-4 Video Verification Model for size conversion of 2:1, 4:1, 5:3 and 5:6. We design 5 filters for the same purpose and compare the performance. The remaining one is very simple to implement. For comparing the filtering performance, we first compare the results of sine wave frequency conversion as an indirect but meaningful comparison. Second. We compute the PSNR of the images obtained from the proposed filters and the ones proposed by MPEG, with reference to the images obtained by using double precision arithmetic and high order filter. The results show that the performance of the proposed filters is almost the same as that of the filters proposed by MPEG. In conclusion, the peroformance of the proposed filters is comparable to that of the ones in MPEG-4, while requiring lower hardware complexity and providing high operating speed.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1288-1298
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• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.661-674
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• 2000

The main memory DBMS(MMDBMS) efficiently supports various database applications that require high performance since it employs main memory rather than disk as a primary storage. In this paper, we discuss theexperiences obtained in developing the index manager of the Tachyon, a next-generation MMDBMS. The indexmanager is an essential sub-component of the DBMS used to speed up the retrieval of objects from a largevolume of a database in response to a certain search condition. Previous research efforts on indexing proposed various index structures. However, they hardly dealt with the practical issues occured in implementating an index manager on a target DBMS. In this paper, we touch these issues and present our experiences in developing the index manager on the Tachyon as solutions. The main issues touched are (1) compact representation of an indexentry, (2) support of variable-length keys, (3) support of multiple-attribute keys, (4) support of duplicated keys,(5) definition of external APls, (6) concurrency control, and (7) backup and recovery. We believe that ourcontribution would help MMDBMS developers highly reduce their trial-and-errors.

• Journal of Arbitration Studies
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• v.24 no.4
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• pp.29-47
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• 2014

In recent years, with the rapid development of electronic commerce, companies engaging in e-commerce want to take advantage of fast and easy way to solve ever-growing disputes online. South Korea's e-commerce disputes are mainly solved by mediation process of Korea E-commerce Mediation Committee. The whole process of online mediation can be carried out by the network, with the advantages of high efficiency and speed. On the other hand, the introduction of CIETAC's online Arbitration Rules in China meets the actual needs. Especially the requirement of hearing trials' procedures should be easier and faster, making the dispute can be resolved in a short time. Furthermore, the whole process from applying to ruling is conducted online, which meets the needs of e-commerce business that want to solve the disputes faster and more efficient. In addition, the cost of online arbitration is much lower than the average arbitrations. The implementation of the CIETAC's Online Arbitration Rules, will further promote the development of e-commerce in China. With the increase of trade volume between China and Korea, the e-business are also increasing. Although South Korea has not yet implemented online arbitration until now, CIETAC's effort for combining arbitration and mediation have good implications for development Korea's e-commerce online dispute system to promote e-Commerce between Korea and China.