• Proceedings of the KSR Conference
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• 2008.06a
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• pp.883-891
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• 2008

The design shows the high-technology of the High Speed Train and its renovated services which is still to be solved. This research presents the process held in approaching the design of the streamline nose using the ‘Image Implementation Technique’. The image that has been brought out through the ‘Image Implementation Technique’ and applied to 'Idea-Creation' and 'Idea-Embodiment' is in order to embody the identity of the nose. We have drawn design and form elements through scientific and analytic approach, bringing up the image of the nose.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.1
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• pp.18-27
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• 2002

This paper presents an implementation of digital high-performance speed sensorless control system of an induction motor drives with Direct Torque Control(DTC). The system consists of closed loop stator flux and torque observer, speed and torque estimators, two hysteresis controllers, an optimal switching look-up table, IGBT voltage source inverter, and TMS320C31 DSP controller board. The stator flux observer is based on the combined current and voltage model with stator flux feedback adaptive control for wide speed range. The speed estimator is using the model reference adaptive system(MRAS) with rotor flux linkages for speed turning signal estimation. In order to prove the suggested speed sensorless control algorithm, and to obtain a high-dynamic robust adaptive performance, we have some simulations and actual experiments at low(20rpm) and high(1000rpm) speed areas. The developed speed sensorless system are shown a good speed control response characteristic, and high performance features using 2.2[kW] general purposed induction motor.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2203-2205
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• 2003

In this thesis, it is a purpose to carry out speed control of DC servo motor without using encoder and the resolver which are speed sensor of DC servo motor and it should use estimate algorithm or observer and must assume a speed in order to control speed sensorless. Therefore, high gain observer was designed to estimate rotor speed of DC servo motor and it carries out speed control from the feedback of the speed that assumed done in the thesis. Also, implementation used easy PI controller in speed-controller of DC motor though it was simple. It is compared estimate performance of Luenberger and high gain observer in a way of computer simulation in order to verify performance of the high gain observer which proposed in this thesis, and proved excellency of the high gain observer. And the thesis proved that smooth speed sensorless control of DC servo motor was implemented in invariable driving.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.45-54
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• 2003

Turbo compressor needs high speed rotation of impeller in structure, high rated gearbox and conventional induction motor. This mechanical system increased the moment of inertia and mechanical friction loss. Resently, the study of turbo compressor applied super high speed motor and drive, removing gearbox made its sire small and mechanical friction loss minimum. This paper describes the implementation of the vector control schemes for a variable-speed 131㎾ PMSM(Permanent Magnet Synchronous Motor) drive in super-high speed application.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1263-1270
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• 2000

The operation frequency of High-speed Communication System becomes very fast with the advanced technology of VLSI chips and system implementation. There may exist various types of noise sources degrading the signal integrity in this system. The present main system is made of backplane, so faults can be brought whenever a board is removed, replaced or added. This backplane boards testing is a very important process to verify the operation of system. firstly, we model the effects of the internal noises in the High-speed Communication System to the signal line and propose a new design method to minimize these effects. For the design methodology, we derive the characterization value for each mode land them construct the optimal simulation model. We compare the result of own proposing method with that fo the existing methods, through simulation and show that the quality of High-speed Communication System is significantly enhanced. Secondary our proposing BIST for the Backplane Boards Testing is designed to guarantee that there is no fault in the high-speed communication system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.55-64
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• 2004

In this paper, we propose an efficient FFT algorithm for high speed multimedia communication systems, and present its pipeline implementation results. Since the proposed algorithm is based on the radix-4 butterfly unit, the processing rate can be twice as fast as that based on the radix-2$^3$ algorithm. Also, its implementation is more area-efficient than the implementation from conventional radix-4 algorithm due to reduced number of nontrivial multipliers like using the radix-23 algorithm. In order to compare the proposed algorithm with the conventional radix-4 algorithm, the 64-point MDC pipelined FFT processor based on the proposed algorithm was implemented. After the logic synthesis using 0.6${\mu}{\textrm}{m}$ technology, the logic gate count for the processor with the proposed algorithm is only about 70% of that for the processor with the conventional radix-4 algorithm. Since the proposed algorithm can be achieve higher processing rate and better efficiency than the conventional algorithm, it is very suitable for the high speed multimedia communication systems such as WLAN, DAB, DVB, and ADSL/VDSL systems.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.109-112
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• 2000

The satellite communications are expected to play an important role to provide broadband multimedia services in the 21st century. According to this requirements, this paper describes the design and implementation of ATM-based high speed satellite modem ASIC chipset. The ASIC chip consists of three main parts, CODEC, Modulator and Demodulator. It supports burst and continuous mode operation with TDMA frame consisted of Reference bursts, Inbound burst, and Traffic burst. The maximum transmission rate is OC-3 (155Mbps) and the maximum operating clock speed is 220MHz. This ASIC chip was implemented with 0.25um CMOS technology.

• International journal of advanced smart convergence
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• v.6 no.1
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• pp.68-75
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• 2017

In this paper, a particular application of digital photos, remote sensing, remote shooting air moving, high-resolution and high compression of medical images required by remote shooting of JPEG2000 standard applied in the field of hardware design, production was implemented. JPEG2000 standard for image compression using the software implementation of the processing speed is very slow compared to conventional JPEG disadvantages, and also the standard of JPEG2000 DWT (Discrete wavelet transform) to improve the level of compression for image data if processing speed is a phenomenon that has degraded. In order to solve these JPEG2000 compression / decompression groups were designed and applied. In this paper, the optimal JPEG2000 compression / reservoir hardware by changing the level for still image compression, faster computation speed and quality has shown improvement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4C
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• pp.379-388
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• 2007

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improve the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.85-86
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• 2007

In this paper, a Radix-8 structure for high-speed FFT is proposed. Even throughput of the Radix-8 FFT is twice than that of the Radix-4 FFT, implementation area of the Radix-8 is larger than that of Radix-4 FFT. But, implementation area of the proposed Radix-8 FFT was reduced by using DA(Distributed Arithmetic) for multiplication. The Verilog-HDL coding results for the proposed FFT structure show 49.2% cell area increment comparison with those of the conventional Radix-4 FFT structure. Namely, to speed up twice, 49.2% of area cost is required. In case of same throughput, power consumption of the proposed structure is reduced by 25.4%.