• Title/Summary/Keyword: High-Speed implementation

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Measurement of Hysteresis in PZT-Type Tunable Filters Utilizing OFDR (OFDR을 이용한 PZT형 파장가변 필터의 이력 측정)

  • Park, Do-Hyun;Yeh, Yun-Hae
    • Korean Journal of Optics and Photonics
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    • v.19 no.1
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    • pp.36-42
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    • 2008
  • Implementation of a wavelength-swept source with constant tuning rate adopting a PZT-type tunable filter, requires the knowledge of hysteresis of the filter used. The hysteresis must be considered to avoid any degradation in resolution of the optical frequency domain reflectometry (OFDR) system. An optical spectrum analyzer (OSA) could be used to do the hysteresis measurement, but its measurement time is too long for the high-speed driving conditions for the filter. We proposed a new hysteresis measurement method based on OFDR, which could measure the hysteresis in a real driving condition. A hysteresis measurement apparatus consisted of wavelength-swept source, interferometer, signal processing unit, and PC program is built and used to do the measurement. It is concluded that the new method is useful in the measurement of hysteresis at real driving conditions by successfully implementing a swept-wavelength source whose wavelength change is linear in time.

A Scalable Word-based RSA Cryptoprocessor with PCI Interface Using Pseudo Carry Look-ahead Adder (가상 캐리 예측 덧셈기와 PCI 인터페이스를 갖는 분할형 워드 기반 RSA 암호 칩의 설계)

  • Gwon, Taek-Won;Choe, Jun-Rim
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.8
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    • pp.34-41
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    • 2002
  • This paper describes a scalable implementation method of a word-based RSA cryptoprocessor using pseudo carry look-ahead adder The basic organization of the modular multiplier consists of two layers of carry-save adders (CSA) and a reduced carry generation and Propagation scheme called the pseudo carry look-ahead adder for the high-speed final addition. The proposed modular multiplier does not need complicated shift and alignment blocks to generate the next word at each clock cycle. Therefore, the proposed architecture reduces the hardware resources and speeds up the modular computation. We implemented a single-chip 1024-bit RSA cryptoprocessor based on the word-based modular multiplier with 256 datapaths in 0.5${\mu}{\textrm}{m}$ SOG technology after verifying the proposed architectures using FPGA with PCI bus.

Implementation of a Communication Algorithm between Actuator Controller and Manufacturing System (제조 시스템과 제어기 사이의 통신알고리즘 구현에 관한 연구)

  • Jeong, Hwa-Young;Hong, Bong-Hwa;Kim, Eun-Won
    • 전자공학회논문지 IE
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    • v.46 no.2
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    • pp.46-52
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    • 2009
  • The manufacturing system was used to communicate between controller and GUI system by RS232C. The controller is deal with processing the equipments such as cylinders, motors, sensors, and so on. The Gill system received the signal from actuator controller by direct communication ways, RS232C, and presented the data to user to analyze the all of status for manufacturing system. In this point, it is important that communication use the RS232C. The way is helpful to be able to reduce cost, have simple structure, and easily maintain the stable communication status. Otherwise, the way has some problem to loss signal or data under the high speed communication. So it needs to complement the communication process to without loss data. In this research, we made the communication algorithm and implement the process to reduce losing data when it send or receive the signal using RS232C between controller and manufacturing system.

Construction of High-Speed Parallel Multiplier on Finite Fields GF(3m) (유한체 GF(3m)상의 고속 병렬 승산기의 구성)

  • Choi, Yong-Seok;Park, Seung-Yong;Seong, Hyeon-Kyeong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.3
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    • pp.510-520
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    • 2011
  • In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and compose the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells that have a mod(3) addition gate and a mod(3) multiplication gate. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

On the Implementation of an Advanced Judgement Algorithm for Contact Loss of Catenary System (전차선의 집전상태 판단 알고리즘 구현)

  • Park, Young;Jung, Ho-Sung;Yun, Il-Kwon;Kim, Wonha
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.63 no.6
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    • pp.850-854
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    • 2014
  • Analyzing dynamic performance between pantograph and contact wire depends on mechanical and electrical conditions such as contact force, currents, aerodynamics of pantograph and tension of overhead contact wire. For the characteristic of dynamic performance between pantograph and overhead contact wire, various evaluation systems are used to measuring of the interaction of the contact line and the pantograph. Among the various methods, the contact force and percentage of arcing are intended to prove the safety and the quality of the current collection system on the train. However, these methods are only capable of measuring on the train which are installed measurement systems. Therefore in this paper, a track-side monitoring system was implemented to measure electrical characteristics from active overhead contact wire systems in order to constantly estimate current collection performance of railway operation. In addition, a method to analyze loss of contact phenomena was proposed. According to simulation results, the proposed system was capable of measuring abnormal electrical behavior of pantograph and contact wires on the track-side. The advantage of the proposed system is possible to detect loss of contact or any other electrical abnormalities of all types of trains within sections from sub to sub without the need to install any on-board equipment on trains.

High-Speed Korean Address Searching System for Efficient Delivery Point Code Generation (효율적인 순로코드 발생을 위한 고속 한글 주소검색 시스템 개발)

  • Kim, Gyeong-Hwan;Lee, Seok-Goo;Shin, Mi-Young;Nam, Yun-Seok
    • The KIPS Transactions:PartD
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    • v.8D no.3
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    • pp.273-284
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    • 2001
  • A systematic approach for interpreting Korean addresses based on postal code is presented in this paper. The implementation is focused on producing the final delivery point code from various types of address recognized. There are two stages in the address interpretation : 1) agreement verification between the recognized postal code and upper part of the address and 2) analysis of lower part of the address. In the agreement verification procedure, the recognized postal code is used as the key to the address dictionary and each of the retrieved addresses is compared with the words in the recognized address. As the result, the boundary between the upper part and the lower part is located. The confusion matrix, which is introduced to correct possible mis-recognized characters, is applied to improve the performance of the process. In the procedure for interpreting the lower part address, a delivery code is assigned using the house number and/or the building name. Several rules for the interpretation have been developed based on the real addresses collected. Experiments have been performed to evaluate the proposed approach using addresses collected from Kwangju and Pusan areas.

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LTE-Based Macro Base Station Platform Architecture (LTE 기반 Macro 기지국 Platform 구조 연구)

  • Jeong, Chan-Bok;Bae, Hyeon-Deok
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39C no.9
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    • pp.861-869
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    • 2014
  • This paper shows the research of a platform architecture relates to the LTE-based macro basestation; the proposed platform architecture is designed with the interface between the baseband signal and IF (Intermediate Frequency) per codeword. Using this method, we can smoothly transmit/receive a large amounts of data regardless of the number of antenna in a macro base station which is used technology such as massive MIMO. In this paper, We analyzed the evolution of LTE technology and the trend in the development of the LTE-based system. For validation of the proposed architecture, we compare the general architecture of a conventional with the proposed architecture. From the calculation results of transmission quantity data, we see that the proposed architecture can give better performance than the existing architecture. By presenting this architecture, we hope to provide a new foundation for Design and Implementation of a LTE base station platform which is used technology such as massive MIMO, carrier aggregation (CA), coordinated multi point (CoMP).

Implementation of FlexRay Communication Controller Protocol and its Application to a Robot System (FlexRay 프로토콜 설계 및 로봇 시스템 응용)

  • Kang, Hyun-Soo;Xu, Yi-Nan;Kim, Yong-Eun;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.6
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    • pp.1-7
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    • 2008
  • FlexRay is a new standard of network communication system which provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for future automotive applications. FlexRay communication controller (CC) is the core of the FlexRay protocol specification. In this paper, we first design the FlexRay CC protocol specification and function parts using SDL (Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay CC system was synthesized using Samsung $0.35\;{\mu}m$ technology. It is shown that the designed system can operate in the frequency range above 80 MHz. In addition, to show the validity of the designed FlexRay system the FlexRay system is combined with sound source localization system in Robot applications. The combined system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.

A Study of Core-Stateless Mechanism for Fair Bandwidth Allocation (대역 공평성 보장을 위한 Core-Stateless 기법 연구)

  • Kim, Hwa-Suk;Kim, Sang-Ha;Kim, Young-Bu
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.4C
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    • pp.343-355
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    • 2003
  • Fair bandwidth allocations at routers protect adaptive flows from non-adaptive ones and may simplify end-to end congestion control. However, traditional fair bandwidth allocation mechanisms, like Weighted Fair Queueing and Flow Random Early Drop, maintain state, manage buffera and perform packet scheduling on a per-flow basis. These mechanisms are more complex and less scalable than simple FIFO queueing when they are used in the interi or of a high-speed network. Recently, to overcome the implementation complexity problem and address the scalability and robustness, several fair bandwidth allocation mechanisms without per-flow state in the interior routers are proposed. Core-Stateless Fair Queueing and Rainbow Fair Queuing are approximates fair queueing in the core-stateless networks. In this paper, we proposed simple Layered Fair Queueing (SLFQ), another core-stateless mechanism to approximate fair bandwidth allocation without per-flow state. SLFQ use simple layered scheme for packet labeling and has simpler packet dropping algorithm than other core-stateless fair bandwidth allocation mechanisms. We presente simulations and evaluated the performance of SLFQ in comparison to other schemes. We also discussed other are as to which SLFQ is applicable.

Design of Lightweight Artificial Intelligence System for Multimodal Signal Processing (멀티모달 신호처리를 위한 경량 인공지능 시스템 설계)

  • Kim, Byung-Soo;Lee, Jea-Hack;Hwang, Tae-Ho;Kim, Dong-Sun
    • The Journal of the Korea institute of electronic communication sciences
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    • v.13 no.5
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    • pp.1037-1042
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    • 2018
  • The neuromorphic technology has been researched for decades, which learns and processes the information by imitating the human brain. The hardware implementations of neuromorphic systems are configured with highly parallel processing structures and a number of simple computational units. It can achieve high processing speed, low power consumption, and low hardware complexity. Recently, the interests of the neuromorphic technology for low power and small embedded systems have been increasing rapidly. To implement low-complexity hardware, it is necessary to reduce input data dimension without accuracy loss. This paper proposed a low-complexity artificial intelligent engine which consists of parallel neuron engines and a feature extractor. A artificial intelligent engine has a number of neuron engines and its controller to process multimodal sensor data. We verified the performance of the proposed neuron engine including the designed artificial intelligent engines, the feature extractor, and a Micro Controller Unit(MCU).