• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.29-29
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• 2000

This paper describes the design and implementation of a high-speed navigation computer to achieve precision navigation performance with Strapdown INS. The navigation computer inputs are velocity and angular increment data from the ISA at the signal of the 2404Hz interrupt and performs the removal of gyro block motion and the compensation of high dynamic errors at the 200Hz. For high-speed and high-accuracy, the computer consists of the 68040 micro-processor, 128k Memories, FPGAs, and so on. We show that the computer satisfies the required performance by In-Run navigation tests.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.1137-1142
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• 2008

In this paper, an effect on power conversion unit in high-speed railway vehicle by loss of contact between a catenary system and pantograph suppling electrical power to high-speed railway vehicle are investigated. One of the most important needs accompanied by increasing the speed of high-speed railway vehicle is reduced that arc phenomenon by loss of contact brings out EMI. in case of high-speed railway vehicle using electrical power, as comparison with diesel rolling stock, PLD(Power Line Disturbance) such as harmonic, transient voltage and current, EMI, dummy signal injection etc usually occur. To analysis the effect on loss of contact, it is necessary electrical modeling system between the contact line and the pantograph according to the loss of contact. Therefore analytical model of a contact line and a pantograph is constructed to simulate the behaviour of loss of contact. The reliability of the modeling system is verified by simulation implementation on kinds of loss of contact.

• Proceedings of the KSR Conference
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• 2011.10a
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• pp.1320-1326
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• 2011

The maximum speed of high-speed rail is restricted to various factors such as track condition including slope and radius, tunnel and dynamic stability of vehicle. Among the various factors, traction effort and resistance to motion is principal and basic factor. In addition, at high speed over 300km/h, aerodynamic drag amounts up to 80% of resistance to motion, that it can be said that aerodynamic drag is the most important factor to decide the maximum speed of high-speed rail system. This paper deals with a measure to increase the maximum speed of high-speed train by reducing aerodynamic drag. The traction effort curve and resistance to motion curve of existing high-speed train under development has been employed to set up the target of aerodynamic drag reduction to reach up to 500km/h without modification traction system. In addition, the contribution of various sources of aerodynamic drag to total value has been analyzed and the strategy for implementation of aerodynamic drag reduction has been discussed based on the aerodynamic simulation results around the train using computational fluid dynamics.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1029-1032
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• 1998

In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG $0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.5
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• pp.162-167
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• 1994

The binary image normalization method in image processing can be used in several fields, Especially, its high speed processing method and its hardware implmentation is more useful, A normalization process of each character in character recognition requires a lot of processing time. Therefore, the research was done as a part of high speed process of OCR (optical character reader) implementation as a pipeline structure with host computer in hardware to give temporal parallism. For normalization process, general purpose CPU,MC68000, was used to implement it. As a result of experiment, the normalization speed of the hardware is sufficient to implement high speed OCR which the recognition speed is over 140 characters per second.

• Journal of the Semiconductor & Display Technology
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• v.13 no.1
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• pp.73-81
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• 2014

In this paper, high-speed Hybrid MAC (Medium Access Control layer) implementation suitable for smart grid applications is researched. MB-OFDM (Multi-Band Orthogonal Frequency Division Multiplexing) is considered for high-speed communication method in smart grid application. In this paper, the MAC adopts the distributed network managing method. Also, the MB-OFDM merit of high-speed transfer rate of up to 480Mbps must be supported. Hence, this paper presents an efficient hardware-software integration (co-design) method in order to realize a high- speed transmission, and a realizing method of distribution network. Finally, MAC performance and reliability based on MB-OFDM PHY (PHYsical layer) are confirmed through simulation and emulation.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.635-638
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• 2002

Blowfish is a symmetric block cipher that can be used as a drop-in replacement fur DES or IDEA. It takes a variable-length key, from 32bit to 448bit, making it ideal for both domestic and exportable use. This paper is somewhere middle-of-the-line, where this paper made significant tradeoffs between speed, size and ease of implementation. The main focus was to make an implementation that was usable, moderately compact, and would still run at an acceptable clock speed. For the real time process of blowfish, it is required that high-speed operation and small size hardware. So, A structure of new adders constructed in this study has all advantages abstracted from other adders. As for this new adder, area cost increases by 1.06 times and operation speed increases by 1.42 times.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.247-251
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• 2021

We propose a protocol for Ethernet-based industrial real-time communication networks. In the protocol, the master periodically transmits control frames to all slaves, and the ring-type network topology is selected to achieve high-speed transmission speed. The proposed protocol is implemented in the form of both firmware and Linux kernel modules. To improve the transmission speed, the MAC address table is disabled in the firmware implementation, and the NAPI function of the Ethernet driver is removed in the Linux kernel module implementation. A network experiment environment is built with four ARM processor-based embedded systems and network operation experiments are performed for various frame sizes. From the experimental results, it is verified that the proposed protocol normally operates, and the firmware implementation shows better transmission speed than the Linux kernel module implementation.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.169-170
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• 2012

This paper presents implementation of digital phase controller for thyristor by using FPGA (Field Programmable Gate Array) in HVDC system. Implementation of digital HVDC system is possible by using superior digital simulator such as RTDS (Real Time Digital Simulator). But thyristor phase controller is typically implemented by analog circuit, because it is difficult to implement the phase controller with low operating speed of RTDS. To guarantee high control performance, phase controller needs fast operating speed. This paper presents FPGA based digital phase controller to obtain high speed and high performance. The entire digital simulation of the HVDC system is also implemented by interfacing between FPGA based phase controller and RTDS. Proposed digital HVDC simulator is verified through RTDS simulation.