• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 1993.10a
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• pp.656-665
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• 1993

Two types of baby corn silk detachment systems called fixing and moving baby corn and based on applying frictional force on the silk were developed and evaluated. In the fixing mode the baby corn was fixed on a pin and a hollow frictional cylinder was moved concentrically and vertically along the baby corn towards the branch end. In the moving mode the baby corn was forced vertically towards the tip to pass through the same silk detachment cylinder. Traveling speeds of the detachment cylinder and the baby corn were 44.5 and 166.9 mm/s. In the fixing mode at silk moisture content of 91 % (w.b) silk detachment efficiencies at low and high speeds were 99.1 and 99.2%. The silk detachment efficiencies in the moving mode at low and high speeds were 96.6 and 98.5%. Damaged baby corn at low speed was less than at high speed in both modes. Minimum damage was nil in the fixing mode at low speed and the maximum was 47.5% in the moving mode at high speed. The damaged was due to ovaries r moval at the base near the joint between the baby corn and the branch.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.10
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• pp.1-12
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• 1993

A multiprocessor system for high-speed processing of hybrid image coding algorithms such as H.261, MPEG, or Digital HDTV is presented in this study. Using a combination of highly parallel 32-bit microprocessor, DCT(Discrete Cosine Transform), and motion detection processor, a new processing module is designed for the implementation of high performance coding system. The sysyem is implemented to allow parallel processing since a single module alone cannot perform hybrid coding algorithms at high speed, and crossbar switch is used to realize various parallel processing architectures by altering interconnections between processing modules within the system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.11
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• pp.1135-1141
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• 2014

Performing wideband DDC while quantizing signal over a wide dynamic range and high speed sampling rate have primarily been implemented in a hardware such as, FPGA or ASIC because of time-consuming job. Real-time wideband DDC SW, even though signal environment changes, adapt to signal environment flexibly and can be reused. In addition, it has a lower price than the hardware implementation. In this paper, we study the system design that can be stored in real time designing a high-speed parallel processing architecture for SW-based wideband DDC. Finally, applying a Ping-Pong Buffering mechanism for receiving a signal in real time and CUDA for a high-speed signal processing, we verify wideband DDC design procedure that meets the signal processing.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.8-18
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• 1993

A multi-font, multi-size and high speed character recognition system is designed. The design principles are simpilcity of algorithm, adaptibility, learnability, hierachical data processing and attention by feed back. For the multi-size character recognition, the extracted character images are normalized. A hierachical classifier classifies the feature vectors. Feature is extracted by applying the directional receptive field after the directional dege filter processing. The hierachical classifier is consist of two pre-classifiers and one decision making classifier. The effect of two pre-classifiers is prediction to the final decision making classifier. With the pre-classifiers, the time to compute the distance of the final classifier is reduced. Recognition rate is 95% for the three documents printed in three kinds of fonts, total 1,700 characters. For high speed implemention, a multiprocessor system with the ring structure of four transputers is implemented, and the recognition speed of 30 characters per second is aquired.

• Laser Solutions
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• v.9 no.2
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• pp.11-15
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• 2006

We report experimental results on the high-speed micromachining using a femtosecond laser (800 nm, 130 fs, 1kHz) and galvanometer scanner system (Raylase, Germany). Periodic hole drilling of silicon and glass with the scan speed of 1-20 mm/s is demonstrated. Finally, we demonstrate the utility of the femtosecond laser application to ITO patterning by using a high-speed femtosecond laser scanner system.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.437-445
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• 2000

The reuse partitioning system in microcellular networks are dropped performance of system because of increase hand-off of high-speed terminal. In this paper, we propose hand-off algorithm to improve the performance of reuse partitioning system using microcell according to the ratio of traffic distribution between innercell and outercell from resource management of high-speed and slowspeed terminal. Also, we compare to RPS and evaluate the teletraffic performance analysis of high-speed and slow-speed terminal through computer simulations that we derive the hand-off probability, call dropping probability.

• Journal of Sensor Science and Technology
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• v.30 no.2
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• pp.82-87
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• 2021

In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

• Transactions of Materials Processing
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• v.33 no.2
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• pp.87-95
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• 2024

The current study aims to prove that high-speed forming has better formability than conventional low-speed forming. Experimentally, the quasi-static forming limit diagram was obtained by Nakajima test, and the dynamic forming limit diagram was measured by electrohydraulic forming. For the experiments, the LS-DYNA was used to create the optimal specimen for electrohydraulic forming. The strain measurement was performed using the ARGUS, and comparison of the forming limit diagrams confirmed that EHF showed better formability than quasi-static forming. Theoretically, the Marciniak-Kuczynski model was used to calculate the theoretical forming limit. Swift hardening function and Cowper Symonds model were applied to predict the forming limits in quasi-static and dynamic status numerically.

• The KIPS Transactions:PartA
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• v.8A no.2
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• pp.147-156
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• 2001

A high performance routing switch is an essential device to either the high performance parallel processing or communication networks that handle multimedia transfer systems such as VOD. The high performance routing chip called STC104 is a typical example in the technical aspect which has 32 bidirectional links of 100Mbps transfer sped. It has exploited new technologies, such as wormhole routing, interval labeling, and adaptive routing method. The high speed router has been applied into some parallel processing system as a single chip. However, its performance over the various interconnection networks with multiple routing chips has not been studied. In this paper, the strucrtures and characteristics of the STC104 have been investigated in order to evaluate the high speed router. Various topology of the STC104, such as meshes, torus, and N-cube are defined and constructed. Algorithms of packet transmission have been proposed based on the interval labeling and the group adaptive routing method implemented in the interconnected network. Multicast algorithms, which are often requited to the processor networks and broadcasting systems, modified from U-mesh and U-torus algorithms have also been proposed overcoming the problems of point-to-point communication.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.