• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1640-1643
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• 2005

This paper presents analysis of dynamic characteristics of a high-speed milling spindle with a drawbar and a built-in motor. The spindle system with a built-in motor can be used to simplify the structure of machine tools, to improve the machining flexibility of machine tools, and to perform the high speed machining. In this system the shaft is usually assumed as a rigid rotor. In this paper, the modal characteristics of drawbar in high-speed milling spindle system due to supporting stiffness between drawbar and shaft and considering the mass and stiffness effects of the built-in motor's rotor are analyzed by numerical method. The result shows enough stiff supports must be provided between shaft and drawbar to prevent occurring drawbar vibration lower than the natural frequency of 1st bending mode of spindle. And considering the mass and stiffness of built-in motor's rotor is important thing to derive more accurate results.

• Journal of the Korean Society for Railway
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• v.8 no.5
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• pp.398-404
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• 2005

In this paper, we introduce the on-line test of the current collection characteristics for HSR 350x(Korea High Speed Train project) that have been performed in the Kyoung-bu high-speed line since 2002. Through the analysis of measured data during on-line test, the variation trend of contact force between pantograph and contact wire of catenary according to the span type, the track conditions and driving patterns is reviewed. In order to analyze the variation trend of contact force, we have checked the span type of catenary in KP 24 - 125 out of Kyoung-bu high speed line and obtained the statistical processing result per each span type. This study shows that the track conditions do not affect on the dynamic performance between pantograph and contact wire catenary, and the span type and the driving pattern are important factors in determining the good interaction between them.

• Transactions of Materials Processing
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• v.17 no.8
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• pp.657-661
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• 2008

Recently, products of electronic industry and related parts are required to have the thickness thinner and thinner to reduce the part weight. To go with this trend, LGP(light guide plate) of LCD-BLU(Liquid Crystal Display-Back Light Unit: It is one of kernel parts of LCD) for cell phone has the thickness of ${\sim}0.3mm$ and the battery case of cell phone has ${\sim}0.25mm$. Accordingly, high speed injection molding is required to mold products which have thinner parts. To achieve high speed injection and proper control of hydraulic unit, various design was applied to conventional injection unit. In the present paper, we concentrated on the molding stability of hydro-mechanical high speed injection machine to make an LGP of 0.3mm thickness.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.6
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• pp.104-110
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• 1994

We proposed a high speed feature extraction algorithm and developed a feature vector extraction chip for high speed character recognition. It is hard to implement a high speed OCR by software alone with statistical method . Thus, the whole recognition process is divided into functional steps, then pipeline processed so that high speed processing is possible with temporal parallelism of the steps. In this paper we discuss the feature extraction step of the functional steps. To extract feature vector, a character image is normalized to 40$\times$40 pixels. Then, it is divided into 5$\times$5 subregions and 4x4 subregions to construct 41 overlapped subregions(10x10 pixels). It requires to execute more than 500 commands to extract a feature vector of a subregion by software. The proposed algorithm, however, requires only 10 cycles since it can extract a feature vector of a columm of subregion in one cycle with array structure. Thus, it is possible to process 12.000 characters per second with the proposed algorithm. The chip is implemented using EPLD and the effectiveness is proved by developing an OCR using it.

• Proceedings of the IEEK Conference
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• 2000.11c
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• pp.47-50
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• 2000

Recently many efforts on the development of automatic processing system for delivery sequence sorting have been performed in ETRI , which requires the use of postal 4-state bar code system to encode delivery points. The 4-state bar code called postal 4-state bar code for high speed processing that has been specifically designed for information processing of logistics and automatic processing of the mail items. This paper describes a method of Reed-Solomon encoding for creating error correction codeword of 4-state bar code.

• Journal of Korea Multimedia Society
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• v.6 no.3
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• pp.488-495
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• 2003

With the development of networks, multimedia communication has expanded its application field. From the remote control for household electric appliances to medicine, games, video conferencing and multimedia chatting, multimedia communication is being used in all parts of our lives. This multimedia communication requires the transmission of a lot of data at high speed. But if the transmission rate of the communication network exceeds the processing speed of being used in the high speed network environment, a bottleneck occurs in each node and deteriorates the performance of the network. This is the main reason for the slow speed of data transmission and packet loss. In this paper, considering the client's processing performance, reception performance was predicted and the way of flow control was shown. The computing performance of relevant Processor and its performance was estimated through the actual implementation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.4
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• pp.389-394
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• 2010

This paper describes the conceptual design of mass memory unit for high speed data processing and mass memory management in the STSAT-3 compared to that of STSAT-2. The FPGA directly controls the data receiving from two payloads with the maximum 100Mbps speed and 32Gb mass memory management to satisfy these requirements. We used SRAM-based FPGA from XILINX having fast operating speed and large logic cells. Therefore, the Triple Modular Redundancy(TMR) and configuration memory scrubbing techniques will also be used to protect FPGA from Single Event Upset(SEU) in space.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.2
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• pp.82-89
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• 2013

A detection method of high precision digital line within image is proposed in this paper. If we set the size of image to $N{\times}N$, in fact it is difficult to use the resulting values that the amount of computation is $O(N^4)$. Multiple algorithms are examined to reduced the amount of computation to $O(N^3)$, while suppressing the degradation of precision. How to detect line from the image processing, after stretching treatment of line segments extracted by Hough transform in the local area of an image is a great way to be able to detect several long or short line at high speed, but this method is slightly less precision in the detection of tilted line segments. In this paper, a line detection method improving the precision detection of tilted line segment is applied to the local area, thereby this method does not reduce the processing speed, while it is high precision method for detecting line segments. The experimental results confirm that the proposed method can detect a high precision line in a shorter period of time, compared with the existing methods.

• The Transactions of the Korea Information Processing Society
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• v.4 no.12
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• pp.3111-3122
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• 1997

Since the advent of an information era, the traffic of communication has been remarkably increasing and the information service has gradually become speedy and popular. With these trends, it is necessary to extend the utilization of existing twist pair cables for PSTN(Public Switched Telephone Network) to provide high speed data services for telephone subscribers, In this paper, we have studied on a structure of discrete multi-tone ADSL(Asymmetric Digital Subscriber Lines) system which can support high speed multimedia service using a twist pair cable, and analyzed the transmission performance by computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1046-1055
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• 1994

In this paper, to design high speed 1 line VRAM(Video RAM) suitable for image signal processing with ASIC(Application Specific IC) method, the VRAM memory core has been designed using 3-TR dual-port dynamic cell which has excellent access time and integration characteristics. High speed pipeline operation was attained by separating the first row from the subarray 1 memory core and the simultaneous I/Q operation for a selected single address was made possible by adopting data-latch scheme. Peripheral circuits were designed implementing address selector and 1/2V voltage generator. Integrated ASIC has been optimized using 1.5[ m] CMOS design rule.