• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• Journal of electromagnetic engineering and science
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• v.4 no.2
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• pp.56-62
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• 2004

We present a multi-Gbit/s digital I/O interface based on RF-modulation and capacitive-coupling over an impedance matched transmission line. The RF-interconnect(RFI) can greatly reduce the digital switching noise and eliminate the dc power dissipation over the channel. It also enables reduced signal amplitude(as low as 200 ㎷) with enhanced data rate and affordable circuit overhead. This paper addresses the system advantages and implementation issues of RFI. A prototype on-chip RFI transceiver is implemented in 0.18-${\mu}{\textrm}{m}$ CMOS. It demonstrates a maximum data rate of 2.2 Gbit/s via 10.5-㎓ RF-modulation. The RFI can be very instrumental for future high-speed inter- and intra-ULSI data links.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.110-113
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• 2003

In this paper, the multi-channel high speed data acquisition system is implemented. This high speed signal processing system for 3-D image display is applicable to the manipulation of a medical image processing, multimedia data and various fields of digital image processing. In order to convert the analog signal into digital one, A/D conversion circuit is designed. PCI interface method is designed and implemented, which is capable of transmission a large amount of data to computer. In order to, especially, channel extendibility of images acquisition, bus communication method is selected. By using this bus method, we can interface each module effectively. In this paper, 32-channel A/D conversion and PCI interface system for 3-dimensional and real-time display of the retina image is developed. The 32-channel image acquisition system and high speed data transmission system developed in this paper is applicable to not only medical image processing as 3-D representation of retina image but also various fields of industrial image processing in which the multi-point realtime image acquisition system is needed.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.1
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• pp.33-41
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• 2019

We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.463-470
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• 2014

A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.75-80
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• 1992

This paper deals with the design scheme of the custom control circuit for optimizing the interface of peripheral devices to general-purpose controllers for the high speed digital system. When the various peripheral devices such as memory, I/O devices and buffers which operate at low speed are interfaced to the microprocessor which operates at high speed, inserting the proper wait state to the processor is required. The proposed scheme designed with random logic may be applied to the high performance graphic system like the X-terminal. This circuit provides the flexibility and system independancy for the optimum digital system design.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.251-254
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• 2003

DMB is a next-generation multimedia broadcasting system that not only enables digital broadcasting services such as transmission of CD-duality audio, traffic information, and real-time stock information, but also allows reception of high-quality digital TV in high-speed driving conditions. In the DMB system, MPEG-2 TS(Transport Stream) multiplex method and MPEG-4 System SL(Sync Layer) have been selected as the delivery layer. In this paper, an efficient interface scheme between an MPEG-2 TS processing hardware and software-implemented MPEG-4 system within a DMB terminal device is proposed.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.64-68
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• 1997

In this paper, a controller for the linear motor with high speed and stiffness is implemented using SERCOS interface which is a real time communication protocol between the numerical controller(NC) and the motor driver. The proposed controller is mainly composed of current, speed, and position controller, which are designed using the 32-bit DSP(TMS320C31), a high-integrated logic device (EPM7128), and Intelligent Power Module(IPM) to enhance reliability and compactness of the system. The experimental results show the effective performance of the proposed controller for he linear motor with high speed and stiffness.

• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.10-17
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• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.

• Proceedings of the KSR Conference
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• 2011.05a
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• pp.1182-1188
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• 2011

By storing various train information in running high speed train, we can analyze the cause of train accident efficiently. we have developed the smart and high available control method to control and manage the hardware modules. The hardware modules for event recorder consist CPU, Digital Input and Output, Pulse Input, Communication, Control Panel and Crash Protected Memory. The real time operation system is used to totally control and manage the various hardware modules. The main function of control method is collection of train information, calculation of train speed, interface with other on-board control system, storing and retrieving train information, and communication with Control Panel. In Control Panel, it displays the current train speed and the status of event recorder effectively. Also user interface is provided in Control Panel.