• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.2
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• pp.206-211
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• 2010

Since high-speed train is a dynamic load in which electric power is externally supplied, contact loss between the catenary and pantograph occurs. This phenomena including vibrations generates frequently irregular arcs, which, in turn causes EMI. Thus it is very important to develop the approach to reduce arc phenomenon by contact loss, as speed of electric railway vehicle increases. In case of an electric railway vehicle using electrical power, compared with diesel rolling stock, Power Line Disturbance(PLD) such as harmonics, transient voltage and current, Electromagnetic Interference(EMI), and dummy signal injection etc usually occur. In this study, the dynamic characteristics of a contact wire and a pantograph suppling electrical power to high-speed train are investigated with an electrical response point. To implement power line disturbance induced by contact loss phenomenon for high speed train operation, a hardware simulator which considers contact loss between contact wire and pantograph as well as contact wire deviation is developed. It is confirmed by the experiments that contact loss effect is largely dependent on voltage conditions when the contact loss occurs. Also, a passive filter is designed to reduce power disturbance and the designed system is verified by experiment.

• Journal of Advanced Navigation Technology
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• v.18 no.3
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• pp.229-235
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• 2014

This paper presents the Doherty power amplifier with a digitally controlled analog predistorter circuit of Scintera Corp. to produce high power efficiency and high linearity performance. The analog predistorter improves the linearity performance because of controlling amplitude and phase values of input signal in order to improve intermodulation performance of power amplifier. Also, the power amplifier is designed by the Doherty technology to obtain the high efficiency performance. To validate the Scintera's analog predistorter, we are implemented the power amplifier with Doherty method at center frequency 2150 MHz. Compared with the balanced amplifier, the power amplifier is improved above 11% enhanced efficiency and more than 15 dB ACPR improvement.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.314-320
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• 2001

A novel mode of parallel operation of a modular 3-phase AC-DC flyback converter for power factor correction along with tight regulation was recently analyzed and presented. The advantage of the proposed converter does not require expensive high voltage and high current devices that are normally needed in popular boost type 3-phase converter. In this paper the detailed small signal analysis of the modular 3-phase AC-DC flyback converter is provided for control purposes and also experimental results are included to confirm the validity of the analysis.

• Journal of Power System Engineering
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• v.14 no.1
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• pp.5-10
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• 2010

Both the accuracy and stability of the clock get from the GPS receiver are considered in the range of pps. And we verified the system clock stability of a micro-controller system using the pps pulse supplied by the GPS receiver. In complex system of digital processing, the rack of precise timing signal may cause the serious problem or breakdown accident. To get rid of these undesirable problems, we introduced VCXO circuit to a micro-controller system to preserve high accurate clock stability.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.339-342
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• 2002

In this paper, the structure of OFDM system is studied, and causes of inter carrier interference (ICI) are analyzed. Based on analysis, this paper shows a technique to prevent a distortion due to nonlinearity of high Power amplifier. The proposed scheme is a predistorter for high power amplifier linearization in orthogonal frequency division multiplexing (OFDM) system used in wireless local area network(WLAN). This is verified by comparing BER characteristics of OFDM system, between used PD and not used PD.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.39-45
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• 2009

OFDM is used for achieving a high-speed data transmission in mobile wireless communication systems. Conventionally, fast Fourier transform that is the main signal processing of OFDM is implemented using digital signal processing. The DSP FFT LSI requires large power consumption. Current-mode FFT LSI with analog signal processing is one of the best solutions for high speed and low power consumption. However, for the operation of current-mode FFT LSI that has the structure of parallel-input and parallel-output, current-mode serial-to-parallel and parallel-to-serial converter are indispensable. We propose a novel current-mode SPC and PSC and full chip simulation results agree with experimental data. The proposed current-mode SPC and PSC promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.69-72
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• 2001

High-level synthesis generates a structural design that implements the given behavior and satisfies design constraints for area, performance, power consumption, packaging, testing and other criteria. Thus, high-level synthesis generates that register-transfer(RT) level structure from algorithm level description. High-level syntehsis consist of compiling, partitioning, scheduling This paper we study the partitioning process, and analysis the min-cut algorithm and simulated annealing algorithm.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.73-76
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• 2001

High-level synthesis generates a structural design that implements the given behavior and satisfies design constraints for area, performance, power consumption, packaging, testing and other criteria. Thus, high-level synthesis generates that register-transfer(RT) level structure from algorithm level description. High-level synthesis consist of compiling, partitioning, scheduling. In this paper, we proposed the efficient scheduling algorithm that find the number of the functional unit and scheduling into the minimum control step with silicon area resource constrained.

• Proceedings of the Korean Nuclear Society Conference
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• 1995.10a
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• pp.223-229
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• 1995

Loose Par Monitoring System(LPMS) is one of the fundamental diagnostic tools installed in the nuclear power plants. In this paper, recovery process algorithm and model for the corrupted impact signal generated by loose parts is presented. The characteristics of this algorithm can obtain a proper burst signal even though background noise is considerably high level comparing with actual impact signal. To verify performance of the proposed algorithm, we evaluate mathematically signal-to-noise ratio of primary output and noise. The performance of this recovery process algorithm is shown through computer simulation.

• Journal of Semiconductor Engineering
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• v.1 no.2
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• pp.64-73
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• 2020

As CMOS technology scales down, the design of analog signal processing circuit becomes far more difficult because of steadily decreasing supply voltage and smaller intrinsic gain of transistors. With sub-1V supply voltage, the conventional analog signal processing relying on high-gain amplifiers is not an effective solution and different approach has to be sought. One of the promising approaches is "time-domain analog signal processing" which exploits the improving switching speed of transistors in a scaled CMOS technology. In this paper, various time-domain analog signal processing techniques are explained with some experimental results.