• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 전력전자학술대회
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• pp.231-232
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• 2017

This paper describes the design and implementation of a 2.5kW (500V, 5A) simmer circuit that maintains the ionization of xenon gas inside the lamp. The design is based on a LCC resonant converter in continuous conduction mode (CCM) with above resonant frequency to take advantage of high power density from using parasitic elements such as the leakage inductance in a power transformer. In addition, since the converter has current source output characteristics, it is suitable for maintaining ionization of the lamp having the negative resistance load characteristic. To verify this converter design, PSpice modeling was performed. Finally, the developed simmer circuit is verified by a resistive load of rated performance and the Ionization maintenance operation of the xenon flash lamp.

• ETRI Journal
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• 제42권6호
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 춘계학술회의 초록집
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• pp.21-21
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• 2010

(Ba,Sr)$TiO_3$ (BST) thin film with a perovskite structure has potential for the practical application in various functional devices such as nonvolatile-memory components, capacitor, gate insulator of thin-film transistors, and electro-optic devices for display. Normally, the BST thin films derived from sol-gel and sputtering are amorphous or partially crystalline when processed below $600^{\circ}C$. For the purpose of integrating BST thin film directly into a Si-based read-out integrated circuit (ROIC), it is necessary to process the BST film below $400^{\circ}C$. The microstructural and electrical properties of low-temperature crystallized BST film were studied. The BST thin films have been fabricated at $350^{\circ}C$ by UV-assisted rapidly thermal annealing (RTA). The BST films are in a single perovskite phase and have well-defined electrical properties such as high dielectric constant, low dielectric loss, low leakage current density, and high breakdown voltage. Photoexcitation of the organics contained in the sol-gel-derived films by high-intensity UV irradiation facilitates elimination of the organics and formation of the single-crystalline phase films at low temperatures. The amorphous BST thin film was transformed to a highly (h00)-oriented perovskite structure by high oxygen pressure processing (HOPP) at as low as $350^{\circ}C$. The dielectric properties of BST film were comparable to (or even better than) those of the conventionally processed BST films prepared by sputtering or post-annealing at temperature above $600^{\circ}C$. When external pressure was applied to the well-known contractive BST system during annealing, the nucleation energy barrier was reduced; correspondingly, the crystallization temperature decreased. The UV-assisted RTA and HOPP, as compatible with existing MOS technology, let the BST films be integrated into radio-frequency circuit and mixed-signal integrated circuit below the critical temperature of $400^{\circ}C$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.25.2-25.2
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• 2011

Recently, thin film capacitors used for vehicle inverters are small size, high capacitance, fast response, and large capacitance. But its applications were made up of liquid as electrolyte, so its capacitors are limited to low operating temperature range and the polarity. This research proposes using Ni-P alloys by electroless plating as the electrode instead of liquid electrode. Our substrate has a high aspect ratio and complicated shape because of anodic aluminum oxide (AAO). We used AAO because film thickness and effective surface area are depended on for high capacitance. As the metal electrode instead of electrolyte is injected into AAO, the film capacitor has advantages high voltage, wide operating temperature, and excellent frequency property. However, thin film capacitor made by electroless-plated Ni on AAO for full-filling into etched tunnel was limited from optimizing the deposition process so as to prevent open-through pore structures at the electroless plating owing to complicated morphological structure. In this paper, the electroless plating parameters are controlled by temperature in electroless Ni plating for reducing reaction rate. The Electrical properties with I-V and capacitance density were measured. By using nickel electrode, the capacitance density for the etched and Ni electroless plated films was 100 nFcm-2 while that for a film without any etch tunnel was 12.5 nFcm-2. Breakdown voltage and leakage current are improved, as the properties of metal deposition by electroless plating. The synthesized final nanostructures were characterized by scanning electron microscopy (SEM).

• 한국전기전자재료학회논문지
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• 제22권4호
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• pp.350-354
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• 2009

$Al_{2}O_{3}$ thin films were deposited on GaN(0001) by using a Remote Plasma Atomic Layer Deposition(RPALD) technique with a trimethylaluminum(TMA) precursor and oxygen radicals in the temperature range of $25{\sim}500^{\circ}C$. The growth rate per cycle was varied with the substrate temperature from $1.8{\AA}$/cycle at $25^{\circ}C$ to $0.8{\AA}$/cycle at $500^{\circ}C$. The chemical structure of the $Al_{2}O_{3}$ thin films was studied using X-ray photoelectron spectroscopy(XPS). The electrical properties of $Al_{2}O_{3}$/GaN Metal-Insulator-Semiconductor (MIS) capacitor grown at a $300^{\circ}C$ process temperature were excellent, a low electrical leakage current density(${\sim}10^{-10}A/cm^2$ at 1 MV) at room temperature and a high dielectric constant of about 7.2 with a thinner oxide thickness of 12 nm. The interface trap density($D_{it}$) was estimated using a high-frequency C-V method measured at $300^{\circ}C$. These results show that the RPALD technique is an excellent choice for depositing high-quality $Al_{2}O_{3}$ as a Sate dielectric in GaN-based devices.

• 한국광학회지
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• 제19권1호
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• pp.9-14
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• 2008

본 논문에서는 테라헤르츠 대역에서 동작하는 새로운 구조의 Yagi-Uda 안테나를 설계하였다. 제안한 Yagi-Uda 안테나는 안테나의 driver를 반 파장 다이폴이 아닌 전 파장 다이폴을 사용함으로써 공진주파수에서 $2000{\Omega}$ 정도의 높은 입력 저항을 얻을 수 있었다. 바이어스 선에 Photonic Bandgap 구조를 적용하여 바이어스 선로로의 전류누설을 최소화 하였고, 안테나를 얇은 기판에 설계함으로써 기판의 비유전율로 인한 안테나의 임피던스 저하를 막고 Yagi-Uda 안테나 고유의 단방향 지향적인 복사특성을 나타나게 하였다. 따라서 제안한 Yagi-Uda 안테나는 포토믹서와의 임피던스 부정합 문제를 개선하여 테라헤르츠파의 출력을 증가 시킬 수 있을 것이라 예상한다.

• 한국전기전자재료학회논문지
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• 제23권6호
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• pp.449-453
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• 2010

In this paper, the electrical characteristics of Fin-type SONOS(silicon-oxide-nitride-oxide-silicon) flash memory device with different trapping layers are analyzed in depth. Two kinds of trapping layers i.e., silicon nitride($Si_3N_4$) and hafnium oxide($HfO_2$) are applied. Compared to the conventional Fin-type SONOS device using the $Si_3N_4$ trapping layer, the Fin-type SOHOS(silicon-oxide-high-k-oxide-silicon) device using the $HfO_2$ trapping layer shows superior program/erase speed. However, the data retention properties in SOHOS device are worse than the SONOS flash memory device. Degraded data retention in the SOHOS device may be attributed to the tunneling leakage current induced by interface trap states, which are supported by the subthreshold slope and low frequency noise characteristics.

• 전력전자학회논문지
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• 제16권6호
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• pp.542-553
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• 2011

본 논문에서 방전 또는 스파크로 인한 전기화재, 폭발사고 및 감전 사고의 위험 없이 고주파 고전력을 안전하게 전달할 수 있는 새로운 형태의 실용적인 자기케이블을 처음으로 제안하였다. 또한, 케이블 사이에서 발생하는 누설자속에 대한 자기저항을 주변효과(fringe effect)까지 고려하여 정량적으로 해석하였다. 자기케이블에 상쇄코일, 상쇄금속판, 상쇄금속관과 같은 상쇄실드 적용함으로써 자기케이블 사이의 누설자속을 급격히 줄여 콤팩트한 자기케이블을 구현하였고, 장거리 전력전송을 가능하게 하였다. 입력전류 $10A_{rms}$(20kHz)에서 상쇄금속관이 적용된 1.5m길이, 5cm의 케이블 사이의 간격을 갖는 자기케이블로 353.8W의 전력을 68%효율로 전달하였다. 이는 상쇄금속관을 적용하지 않았을 때에 비해 출력전력은 약 25배, 효율은 약 7배 높은 수치다. 본 논문에서는 제안된 자기케이블의 성능 특성을 실험과 자장 시뮬레이션을 통해 분석 및 검증하고 비교하였으며, 기대했던 우수한 성능을 실제로 확인하였다.

• The Korean Journal of Ceramics
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• 제3권4호
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• pp.274-278
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• 1997

(Ba, Sr) TiO$_3$(BST) thin films were prepared on RuO$_2$/Si substrates by rf magnetron sputtering and annealing was followed at temperatures ranging from 550 to 80$0^{\circ}C$ in $N_2$or $O_2$atmosphere. The effects of annealing conditions on the properties of BST film deposited on RuO$_2$bottom electrodes were investigated. It was found that the crystallinity. surface roughness, and grain size of BST films vary with the annealing temperature but they are not dependent upon the annealing atmosphere. The flat region in the current-voltage (I-V) curves of BST capacitors shortened with increasing annealing temperature under both atmospheres. This is believed to be due to the lowering of potential barrier caused by unstable interface and the increase of charge The shortening of the flat region by $O_2$annealing was more severe than that by $N_2$-annealing. As a result, there was no flat region when the films were annealed at 700 and 80$0^{\circ}C$ in $O_2$atmosphere. The dielectric properties of BST films were improved by annealing in either atmosphere. however, a degradation with frequency was observed when the films were annealed at relatively high temperature under $O_2$atmosphere.