• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.4
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• pp.261-266
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• 1998

In developing the high density memory device, the etching of fine pattern is becoming increasingly important. Therefore, definition of ultra fine line and space pattern and minimization of damage and contamination are essential process. Also, the high density plasma in low operating pressure is necessary. The candidates of high density plasma sources are electron cyclotron resonance plasma, helicon wave plasma, helical resonator, and inductively coupled plasma. In this study, planar type magnetized inductively coupled plasma etcher has been built. The density and temperature of Ar plasma are measured as a function of rf power, flow rate, external magnetic field, and pressure. The oxide etch rate and selectivity to polysilicon are measured as the above mentioned conditions and self-bias voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.43-46
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.2
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• pp.17-24
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform new both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of 1011~1021[states/eV/cm2] after a stress voltage. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Journal of the Korean Vacuum Society
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• v.4 no.S2
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• pp.156-162
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• 1995

For a stimulating neural electrode, the charge density should be as large as possible to provide adequate stimulation of the nervous system while allowing for miniaturization of the electrode. Since iridium oxide is able to produce high charge densities while preventing undesirable reactions due to charge storage, it has become a promising material for neural prostheses. Successful production of stable Ir and Ir oxide films on various substrates now limits the use of this material. Ir was deposited on two differently prepared surface of (mirror finish, passivation) surgical Ti-6AI-4V with several methods. Ion beam mixing of sputter deposited Ir films on passivated Ti-6AI-4V produced stable and good adherent Ir films. It was found that the increase in charge density of pure Ir on continuous cyclingis due to the accumulation of the oxide phase ( associated with a large surface area) in which the valence state of iridium changes and the double-layer capacitance increases. This study also showed that the double layer capacitance is equally or even more responsible for the high charge density of anodically formed Ir oxide.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.190-197
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• 1992

In this study we have investigated physical and electrical properties of high temperature oxide (HTO) thin film using dichlorosilane (DCS) gas. This film had low etch rate and excellent step coverage, and its characteristics of Si-O bond were similar to those of thermal oxide. I-V curves also showed similar electrical properties to those of thermally grown oxide (SiO2) while time dependent dielectric breakdown (TDDB) results revealed 1/4 value of thermal oxide. However, defect density was measured to be much lower value than that of thermal oxide.

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.90-94
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• 2015

We stuidied liauid crystal alignment treatment using solution process for making thin oxide layer in liquid crystal display. It is the one of very effient and popular process in making thin oxide layer in electronical industrial fields. Particularly, this process has highly potential value in liquid crystal display industrial fields because it cause automatically induced alignment process without tranditional alignment process in liquid crystal alignment process. We made several different kinds of mol density solutions using strontium oxide solution. And those solutions were treated for solidification layers using annealing process for 2 hours. And we stuided pretilt angle properties of these alignment layers of strontium oxide for clarifying the relationship of liquid crystal molecules and thin strontium oxide layer. And we also tested the existence of strontium oxide thin layer on substrate using XPS measurement. We expected the hig gain of electro-optical properties in liquid crystal display using strontium oxide thin layer because it has high K property material than the other metal-based oxide layers. In this results, we measured 1.447 to 1.613 thresholds volts as 0.1 mol to 0.4 mol density in 0.1 mol density steps. This is significant better characteristics than conventional liquid crystal display as higher than 1.85 thresholds volts. And it make possible to making next-generation liquid crystal display which present low-power consumption and wide gray scale in liquid crystal display.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.253-253
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• 2012

Low temperature SiOx film process has being required for both silicon and oxide (IGZO) based low temperature thin film transistor (TFT) for application of flexible display. In recent decades, from low density and high pressure such as capacitively coupled plasma (CCP) type plasma enhanced chemical vapor deposition (PECVD) to the high density plasma and low pressure such as inductively coupled plasma (ICP) and electron cyclotron resonance (ECR) have been used to researching to obtain high quality silicon oxide (SiOx) thin film at low temperature. However, these plasma deposition devices have limitation of controllability of process condition because process parameters of plasma deposition such as RF power, working pressure and gas ratio influence each other on plasma conditions which non-leanly influence depositing thin film. In compared to these plasma deposition devices, neutral beam assisted chemical vapor deposition (NBaCVD) has advantage of independence of control parameters. The energy of neutral beam (NB) can be controlled independently of other process conditions. In this manner, we obtained NB dependent high crystallized intrinsic and doped silicon thin film at low temperature in our another papers. We examine the properties of the low temperature processed silicon oxide thin films which are fabricated by the NBaCVD. NBaCVD deposition system consists of the internal inductively coupled plasma (ICP) antenna and the reflector. Internal ICP antenna generates high density plasma and reflector generates NB by auger recombination of ions at the surface of metal reflector. During deposition of silicon oxide thin film by using the NBaCVD process with a tungsten reflector, the energetic Neutral Beam (NB) that controlled by the reflector bias believed to help surface reaction. Electrical and structural properties of the silicon oxide are changed by the reflector bias, effectively. We measured the breakdown field and structure property of the Si oxide thin film by analysis of I-V, C-V and FTIR measurement.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.309-314
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• 1999

The magnetized helical resonator plasma etcher has been built. Electron density and temperature were measured as functions of rf source power, axial magnetic field, and pressure. The results show electron density increases as the magnetic field increases and reached $2\times1012cm^{-3}$,/TEX>. The oxide etch rate and selectivity to polysilicon were investigated as the above mentioned conditions and self-bias voltage. We can obtain the much improved oxide etch selectivity to polysilicon (60 : 1) by applying the external axial weak magnetic field in magnetized helical resonator plasma etcher.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.6
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• pp.412-417
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• 2000

High electric field stressed trap distributions were investigated in the thin silicon oxide of polycrystalline silicon gate metal oxide semiconductor capacitors. The transient currents associated with the off time of stressed voltage were used to measure the density and distribution of high voltage stress induced traps. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface in polycrystalline silicon gate metal oxide semiconductor devices. The stress generated trap distributions were relatively uniform the order of $10^{11}$~$10^{12}$ [states/eV/$\textrm{cm}^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}$~$10^{13}$ [states/eV/$\textrm{cm}^2$]. It was appeared that the transient current that flowed when the stress voltages were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.