• 제목/요약/키워드: High Power semiconductor

검색결과 969건 처리시간 0.024초

A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain Comparator

  • Lee, Han-Yeol;Jeong, Dong-Gil;Hwang, Yu-Jeong;Lee, Hyun-Bae;Jang, Young-Chan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권6호
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    • pp.695-702
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    • 2015
  • A 1-V 1.6-GS/s 5.58-ENOB flash ADC with a high-speed time-domain comparator is proposed. The proposed time-domain comparator, which consumes low power, improves the comparison capability in high-speed operations and results in the removal of preamplifiers from the first-stage of the flash ADC. The time interpolation with two factors, implemented using the proposed time-domain comparator array and SR latch array, reduces the area and power consumption. The proposed flash ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1-V supply voltage. The measured DNL and INL are 0.28 and 0.41 LSB, respectively. The SNDR is measured to be 35.37 dB at the Nyquist frequency. The FoM and chip area of the flash ADC are 0.38 pJ/c-s and $620{\times}340{\mu}m^2$, respectively.

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

  • Lee, Seongjoo;Lee, Jangwoo;Song, Minkyu
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권4호
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    • pp.376-382
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    • 2014
  • In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is $2.99mm^2$ and the power dissipation is about 120 mW. The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

차세대 전력반도체 소자 및 패키지 접합 기술 (Recent Overview on Power Semiconductor Devices and Package Module Technology)

  • 김경호;좌성훈
    • 마이크로전자및패키징학회지
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    • 제26권3호
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    • pp.15-22
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    • 2019
  • In these days, importance of the power electronic devices and modules keeps increasing due to electric vehicles and energy saving requirements. However, current silicon-based power devices showed several limitations. Therefore, wide band gap (WBG) semiconductors such as SiC, GaN, and $Ga_2O_3$ have been developed to replace the silicon power devices. WBG devices show superior performances in terms of device operation in harsh environments such as higher temperatures, voltages and switching speed than silicon-based technology. In power devices, the reliability of the devices and module package is the critically important to guarantee the normal operation and lifetime of the devices. In this paper, we reviewed the recent trends of the power devices based on WBG semiconductors as well as expected future technology. We also presented an overview of the recent package module and fabrication technologies such as direct bonded copper and active metal brazing technology. In addition, the recent heat management technologies of the power modules, which should be improved due to the increased power density in high temperature environments, are described.

평균전류모드 플라이백 토폴로지를 이용한 PDP용 고효율 AC-DC 컨버터 및 Hold-up 특성 개선 (High Efficiency AC-DC Converter Using Average-Current Mode Flyback Topology for PDP and Improvement of Hold-up Characteristic)

  • 이경인;임승범;정용민;오은태;이준영
    • 반도체디스플레이기술학회지
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    • 제7권2호
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    • pp.23-27
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    • 2008
  • Recently, regulation for THD (Total Harmonic Distortion) such as IEC 61000-3-2, IEEE 519 is being reinforced about a product which directly connects to AC line in order to prevent distortion of common power source in electronic equipment and electrical machinery. In order to satisfy these regulations, conventional circuits were used two-stage structure attached power factor correction circuit at ahead of converter but this method complicate the circuit and then a number of element increases thereupon the cost of production rises. in this paper, we propose a high efficiency single-stage 300W PFC fly-back converter that improved power factor and efficiency than conventional two-stage power module.

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LGT를 이용한 고온, 고압용 동압 센서 개발 (Development of the high-temperature, high-pressure Dynamic pressure sensor with LGT)

  • 권혁제;이경일;김동수;김영덕;이영태
    • 반도체디스플레이기술학회지
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    • 제11권2호
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    • pp.17-21
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    • 2012
  • This study developed a high-temperature, high-pressure dynamic pressure sensor using LGT(lanthanum gallium tantalate). The sensitivity of the fabricated dynamic pressure sensor was 2.1 mV/kPa and its nonlinearity was 2.5%FS. We confirmed that the high-temperature dynamic pressure sensor operated stably in high-temperature environment at $500^{\circ}C$. The developed dynamic pressure sensor using LGT is expected to be applicable not only to gas turbines but also in various industrial areas in duding airplanes and power stations.

위성 통신 시스템 응용을 위한 우수한 성능의 Ku 대역 2W MMIC 전력증폭기 (High Performance Ku-band 2W MMIC Power Amplifier for Satellite Communications)

  • 류근관;안기범;김성찬
    • 한국정보통신학회논문지
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    • 제18권11호
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    • pp.2697-2702
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    • 2014
  • 본 논문에서는 위성 통신 시스템 응용을 위하여 Ku 대역에서 동작 가능한 2W MMIC (monolithic microwave integrated circuit) 전력증폭기를 개발하였다. 2W MMIC 전력증폭기는 WIN (wireless information networking) semiconductor Corp.의 GaAs 기반 PHEMT (pseudomorphic high electron mobility transistor) 공정을 사용하여 개발되었다. 개발된 Ku 대역 2W MMIC 전력증폭기의 측정결과, 13.75 GHz ~ 14.5 GHz의 동작주파수 범위에서 29 dB 이상의 이득, 33.4 dBm 이상의 포화 출력전력을 얻었다. 특히 전력부가효율은 29 %로 기존에 발표된 GaAs 기반 Ku 대역 2W MMIC 전력증폭기 상용 제품들에 비하여 높은 결과를 얻을 수 있었다.

A 10-bit Current-steering DAC in 0.35-μm CMOS Process

  • Cui, Zhi-Yuan;Piao, Hua-Lan;Kim, Nam-Soo
    • Transactions on Electrical and Electronic Materials
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    • 제10권2호
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    • pp.44-48
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    • 2009
  • A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

Adaptive Synchronous Rectification Control Method for High Efficiency Resonant Converter

  • Kim, Joohoon;Moon, Sangcheol;Kim, Jintae
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2017년도 전력전자학술대회
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    • pp.40-41
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    • 2017
  • New adaptive SR (synchronous rectification) control method is proposed offering high efficiency in entire load conditions for resonant converters, in this paper. Unlike the conventional SR control method where turn-on time of the MOSFETs is varied depending on load conditions due to the stray inductance induced by a lead frame of MOSFET or PCB patterns, the proposed method automatically maintains a time interval between turn-off instance of a MOSFET and zero current instance of a body diode of the MOSFET as a predetermined time, in each switching cycle. Therefore, optimized turn-on time of the MOSFET can be achieved regardless of the leakage inductance. In this paper, the operational principle of proposed control method has been discussed. It has been tested on LLC resonant converter with 240 W to verify the proposed control method.

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