Transactions on Electrical and Electronic Materials

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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A 10-bit Current-steering DAC in 0.35-μm CMOS Process

  • Cui, Zhi-Yuan (Department of Semiconductor Engineering, Chungbuk National University) ;
  • Piao, Hua-Lan (Department of Semiconductor Engineering, Chungbuk National University) ;
  • Kim, Nam-Soo (Department of Semiconductor Engineering, Chungbuk National University)
  • Published : 2009.04.25
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Abstract

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

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References

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