• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.321-326
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• 1992

In this paper, a high performance graphics system is suggested and its hardware architecture and software structure are described. The developed graphics system is a multi-processing system that uses 6 i860 RISC CPU's and supports PHIGS language in a hardware level. The software is programmed with respect to the graphics pipeline and the software modules are distributed into each processor for the optimization of the performance. The implemented graphics system can draw about 100,000 3D polygons second.

• Smart Media Journal
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• v.1 no.1
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• pp.1-9
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• 2012

This Paper proposes an effective SoC hardware architecture implementing a VDP for Full HD TVs. The proposed architecture makes real time video processing possible with supporting efficient bus architecture and flexible interface. Video IP cores in the VDP are designed to provide a high quality of improved image enhancement function. The Avalon interface is adopted to guarantee real-time capability to IPs as well as SoC integration. This leads to reduced design time and also enhanced designer's convenience due to the easiness in IP addition, deletion, and revision for IP verification and SoC integration. The embedded software makes it possible to implement flexible real-time system by controlling setting parameter details and data transmitting schemes in real-time. The proposed VDP SoC design is implemented on Cyclon III SoPC platform. The experimental results show that our proposed architecture of the VDP SoC successfully provides required quality of Video image by converting SD level input to Full HD level image.

• Korean Journal of Computational Design and Engineering
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• v.15 no.4
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• pp.279-288
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• 2010

In this paper, a DEVS(Discrete EVent Systems Specification)-HLA(High Level Architecture) interface was developed in order to perform the simulation using the combined discrete event and discrete time simulation model architecture in a distributed environment. The developed interface connects the combined simulation model with the HLA/RTI(Run-Time Infrastructure) which is an international standard middleware for distributed simulation. The interface consists of an interface model, a model interpreter, and a distributed environment interpreter. The interface model was defined by using the combined simulation architecture in order to easily connect the existing combined simulation model without modification with the HLA/RTI. The model interpreter takes charge of data transmission between the interface model and the combined simulation model. The distributed environment interpreter takes charge of data transmission between the interface model and the HLA/RTI. To evaluate the applicability of the developed interface, it was applied to the diving simulation of a submarine in a distributed environment. The result shows that a simulation result in a distributed environment using the interface is the same to the result in a single computing environment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.224-236
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• 2013

This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.

• Journal of the Korean Institute of Landscape Architecture
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• v.23 no.2
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• pp.213-222
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• 1995

To increase the night use level, this study was analyzed perception of users about the public safety, and extracted main variables which were influencing public safety. The public safety was evaluated by the actual (on site) and nonactual users (off site) and the Delphi method. The night users of female and the elders were relatively more than male and the young respectively as compared with day. Walking was predominant in approaching means. In public safety ratings, $\boxDr$vuknerability to violence$\boxUl$varied accoding to sex, income, education, marriage, job, age. $\boxDr$crowding, $\boxDr$noise$\boxUl$ were important variables in satisfying users at night. $\boxDr$Lack of surveillance, $\boxDr$harassment of other person$\boxUl$, $\boxDr$rowdy behavior in poorer visibility$\boxUl$, $\boxDr$fear in lower intensity of light$\boxUl$ and $\boxDr$vulnerability to violence$\boxUl$stood high , so it is required guarantee of security guard to enhance the park use at night Although the ratings between field and indoor evaluation were somewhat different the variables had so similiar rant.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.532-535
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• 2004

Architecture generation is the first step in the design of software systems. Most of the qualities that the final software system possesses are usually decided at the architecture development stage itself. Thus, if the final system should be usable, testable, secure, high performance, mobile and adaptable, then these qualities or non­functional requirements should be engineered into the architecture itself. In particular, adaptability is emerging as an important attribute required by almost all software systems. The machinery and tools in the remote site surveillance and connects intelligence information machinery and tools at Internet. We need the server which uses different embedded operating system to become private use. With the progress of information-oriented society, many device with advanced technologies invented by many companies. However, the current firmware technologies have many problems to meet such high level of new technologies. In this paper, we have successfully ported linux on an embedded system, which is based on intel StrongARM SA-1 1 10 processor, then written several network modules for internet-based network devices.

• KCI Concrete Journal
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• v.14 no.4
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• pp.171-177
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• 2002

Antifungal agents are used to impart antibacterial or bactericidal properties to commodities and various articles used in industries and can be classified into two broad groups i.e organic and inorganic. Inorganic antifungal agents comprise of Ag, Zn, or Cu, etc. These elements tend to exhibit high level of antifungal activities, non-uniform dispersion in substrates, and have poor properties in expensive and cheap adhesiveness. In this study, the organic antifungal agent was used for the purpose of investigating the antifungal activity of antifungal agent activated-cement mortar (AACM) on the aspergilus niger of various fungus which can be easily discovered in the interiors and exteriors of buildings. In addition, an experiment on the basic physical properties of AACM such as compressive and flexural strength was carried out. The conclusion of this investigation revealed that a dosage increase of antifungal agent exhibits a high inhibitory effect on the aspergilus niger, and although there is a slight decrease in the strength of AACM, the strength of AACM was almost equal to that of inactivated cement mortar.

• Journal of the Korean Institute of Landscape Architecture
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• v.33 no.6 s.113
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• pp.40-50
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• 2006

This study was carried out to examine the tree-ring growth characteristics of Zelkova serrata Makino after replanting, for the built-up planting founds for stability of landscaped trees in the reclaimed land from the sea. the factors, many affecting the growths of Zelkova serrata Makino, were the replanting stress and drought. The growth reduction due to replanting and drought occurred in the replanting year and the following year. The mean sensitivity(year-to-year variation) and the coefficient of variation(tree-to-tree variation in a certain year) in tree rings of Zelkova serrate Makino, were higher in the poor soil sites than in the favourable soil ones. And the poor soil sites were the filled ground of improve soil and the covered ground of improve soil and the top ground of big mounding than mounding ground sites, especially soil hardness, alkali soil, high $Na^+\;and\;K^+,\;low\;Ca^{++}\;and\;Mg^{++}$ and T-C were the most crucial. We suggest technique development of the built-up planting ground for stability in the reclaimed land from the sea. The built-up planting grounds in reclaimed land from the sea, should be considered for the use of fair soil with the physical and chemical soil properties, -high level foundation of planting ground, and the prevention of disturbed soil-.

• Journal of the Korea Society for Simulation
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• v.12 no.4
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• pp.41-50
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• 2003

HLA (High Level Architecture) is the object, time, and interface standard that proposed for distribution simulation in the US Department of Defense. The HLA is defined by three components: Rules, the HLA Interface Specification, and the Object Model Template (OMT). The RTI (Run-Time Infrastructure) software implements the interface specification. It provides services to simulation applications. To test whether a RTI software is suitable for the standard and all service was implemented is performed through two phases of processes proposed by DMSO. In this paper, we implement Level One Test Procedures of DMSO and apply to NetCust's RTI software. The experimental results are discussed.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.