• Bulletin of the Korean Chemical Society
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• v.19 no.8
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• pp.847-851
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• 1998

13C, 15N, and 29Si NMR chemical shifts have been computed for selected X-substituted silatranes (X=Cl, F, H, CH3) using Gauge-Including Atomic Orbitals (GIAO) and Continuous Set of Gauge Transformations (CSGT) at the Hartree-Fock level of theory. The isotropic 13C chemical shifts are largely insensitive to substituent-induced structural changes. In this study, the isotropic 13C chemical shifts GIAO and CSGT calculations at the HF/6-31G and HF/6-31G* levels are sufficiently accurate to aid in experimental peak assignments. The isotropic 13C chemical shifts X-substituted silatranes at HF/6-31G* level are approximately 4 ppm different from the experimental values. In contrast, the isotropic 15N and 29Si chemical shifts and the chemical shielding tensors are quite sensitive to substituent-induced structural changes. These trends are consistent with those of the experiment. The 15N chemical shift parameters demonstrate a very clear correlation with Si-N distance, especially when we use the polarization function. Changes in anisotropy, 3a as well as in the 15N isotropic chemical shifts are due primarily to changes in the value of a.. But in case of "Si the correlations are not as clean as for the 15N chemical shift.

• Korean Journal of Materials Research
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• v.8 no.10
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• pp.890-897
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• 1998

The direct wafer bonding between n-InP(001) wafer and the ${Si}_3N_4$(200 nm) film grown on the InP wafer by PECVD method was investigated. The surface states of InP wafer and ${Si}_3N_4$/InP which strongly depend upon the direct wafer bonding strength between them when they are brought into contact, were characterized by the contact angle measurement technique and atomic force microscopy. When InP wafer was etched by $50{\%}$ HF, contact angle was $5^{\circ}$ and RMS roughness was $1.54{\AA}$. When ${Si}_3N_4$ was etched by ammonia solution, RMS roughness was $3.11{\AA}$. The considerable amount of initial bonding strength between InP wafer and ${Si}_3N_4$/InP was observed when the two wafer was contacted after the etching process by $50{\%}$ HF and ammonia solution respectively. The bonded specimen was heat treated in $H^2$ or $N^2$, ambient at the temperature of $580^{\circ}C$-$680^{\circ}C$ for lhr. The bonding state was confirmed by SAT(Scannig Acoustic Tomography). The bonding strength was measured by shear force measurement of ${Si}_3N_4$/InP to InP wafer increased up to the same level of PECVD interface. The direct wafer bonding interface and ${Si}_3N_4$/InP PECVD interface were chracterized by TEM and AES.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.219-219
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• 2010

기존의 플로팅 타입의 메모리는 소자의 소형화에 따른 인접 셀 간의 커플링 현상과 전계에 따른 누설전류의 증가 등과 같은 문제가 발생한다. 이에 대한 해결책으로서 전하 저장 층을 폴리실리콘에서 유전체를 사용하는 SONOS 형태의 메모리와 NFGM (Nano-Floating Gate Memory)연구가 되고 있다. 그러나 높은 구동 전압, 느린 쓰기/지우기 속도 그리고 10년의 전하보존에 대한 리텐션 특성을 만족을 시키지 못하는 문제가 있다. 이러한 문제를 해결 하고자 터널베리어를 엔지니어링 하는 TBM (Tunnel Barrier Engineering Memory) 기술에 대한 연구가 활발히 진행 중이다. TBM 기술은 터널 층을 매우 얇은 다층의 유전체를 사용하여 전계에 따른 터널베리어의 민감도를 증가시킴으로써 빠른 쓰기/지우기 동작이 가능하며, 10년의 전하 보존 특성을 만족 시킬 수 있는 차세대 비휘발성 메모리 기술이다. 또한 고유전율 물질을 터널층으로 이용하면 메모리 특성을 향상 시킬 수가 있다. 일반적으로 TBM 기술에는 VARIOT 구조와 CRESTED 구조로 나눠지는데 본 연구에서는 두 구조의 장점을 가지는 Staggered tunnel barrier 구조를 $Si_3N_4$와 HfAlO을 이용하여 디자인 하였다. 이때 HfO2와 Al2O3의 조성비는 3:1의 조성을 갖는다. $Si_3N_4$와 HfAlO을 각각 3 nm로 적층하여 리세스(Recess) 구조의 트랜지스터를 제작하여 차세대 비휘발성 메모리로써의 가능성을 알아보았다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.410-414
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• 2013

We report the wet etching of titanium nickel (TiNi) films for the production of nano-electro-mechanical (NEM) device. $SiO_2$ and $Si_3N_4$ have been selected as sacrificial layers of TiNi metal and etched with polyethylene glycol and hydrofluoric acid (HF) mixed solution. Volume percentage of HF are varied from 10% to 35% and the etch rate of the $SiO_2$, $Si_3N_4$ and TiNi are reported here. Within the various experiment results, 15% HF mixed polyethylene glycol solution show highest etch ratio between sacrificial layer and TiNi metal. Especially $Si_3N_4$ films shows high etch ratio with TiNi films. Wet etching results are measured with SEM inspection. Therefore, this experiment provides a novel method for TiNi in the nano-electro-mechanical device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.7-8
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• 2008

The memory characteristics of charge trap flash (CTF) with $HfO_2$ charge trap layer were investigated. Especially, we focused on the effects of tunnel barrier engineering consisted of $SiO_2/Si_3N_4/SiO_2$ (ONO) stack or $Si_3N_4/SiO_2/Si_3N_4$ (NON) stack. The programming and erasing characteristics were significantly enhanced by using ONO or NON tunnel barrier. These improvement are due to the increase of tunneling current by using engineered tunnel barrier. As a result, the engineered tunnel barrier is a promising technique for non-volatile flash memory applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.358-358
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• 2010

To improve the programming/erasing speed and leakage current of multiple dielectric stack tunnel barrier engineering (TBE) Non-volatile memory, We propose a new concept called staggered structure of TBE memory. In this study, We fabricated staggered structure capacitor on $Si_3N_4$ stacked HfAlO and measured C-V curve that can observe tunneling characteristic of this device as various annealing temperature compared with that of single layer $SiO_2$ capacitor.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.54-57
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• 2003

[ $HfO_xN_y$ ] films using a hafnium tertiary-butoxide $(Hf[OC(CH_3)_3]_4)$ in plasma and $N_2$ ambient were prepared to improve the thermal stability of hafnium-based gate dielectrics. A 10% nitrogen incorporation into $HfO_2$ films showed a smooth surface morphology and a crystallization temperature as high as $200^{\circ}C$ compared with pure $HfO_2$ films. The $TaN/HfO_xN_y/Si$ capacitors showed a stable capacitance-voltage characteristics even at post-metal annealing temperature of $1000^{\circ}C$ in $N_2$ ambient and a constant value of 1.6 nm EOT (equivalent oxide thickness) irrespective of an increase of PDA and PMA temperature. Leakage current densities of $HfO_xN_y$ capacitors annealed at PDA temperature of 800 and $900^{\circ}C$, respectively were approximately one order of magnitude lower than that of $HfO_2$ capacitors.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.486-489
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• 1987

For longterm conservation of the $Si_3N_4$ gate pH-ISFET, characteristics of ISFET surface treatment with HF and surface coating with paraffin wax were investigated.

• Bulletin of the Korean Chemical Society
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• v.22 no.2
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• pp.159-163
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• 2001

Si3N4 powder has been analyzed by inductively coupled plasma atomic emission spectrometry (ICP-AES). The sample was dissolved by high-pressure acid digestion with HF, H2SO4 (1+1), and HNO3 mix ture. This technique is well suited for the impurity analysis of Si3N4 because the matrix interference is eliminated. A round-robin samples trace elements, such as Ca, W, Co, Al, Fe, Mg, and Na, were determined. For the direct analysis, slurry nebulization of 0.96 mm Si3N4 powder also has been studied by ICP-AES. Emission intensities of Fe were measured as ICP operational conditions were changed. Significant signal difference between slurry particles and aqueous solution was observed in the present experiment. Analytical results of slurry injection and high-pressure acid digestion were compared. For the use of aqueous standard solution for calibration, k-factor was determined to be 1.71 for further application.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.250-251
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• 2009

For the fabrication of a multilevel resist (MLR) based on a very thin amorphous carbon (a-C) layer an $Si_{3}N_{4}$ hard-mask layer, the selective etching of the $Si_{3}N_{4}$ layer using physical-vapor-deposited (PVD) a-C mask was investigated in a dual-frequency superimposed capacitively coupled plasma etcher by varying the following process parameters in $CH_{2}F_{2}/H_{2}/Ar$ plasmas : HF/LF powr ratio ($P_{HF}/P_{LF}$), and $CH_{2}F_{2}$ and $H_2$ flow rates. It was found that infinitely high etch selectivities of the $Si_{3}N_{4}$ layers to the PVD a-C on both the blanket and patterned wafers could be obtained for certain gas flow conditions. The $H_2$ and $CH_{2}F_{2}$ flow ratio was found to play a critical role in determining the process window for infinite $Si_{3}N_{4}$/PVDa-C etch selectivity, due to the change in the degree of polymerization. Etching of ArF PR/BARC/$SiO_x$/PVDa-C/$Si_{3}N_{4}$ MLR structure supported the possibility of using a very thin PVD a-C layer as an etch-mask layer for the $Si_{3}N_{4}$ layer.